03-06-2019 06:39 PM - edited 03-06-2019 06:40 PM
I have tried to find the similar question in this forum.
I find the link below.
But it seems the problem didn't be solved.
I got the same problem
I have tried to write form 0~1000 to address and data
Then I read from address 0 to address 1000
I got the value begin from 9XX 9XX ...1000 0 8 16
I have treid
1. write data in other address which is continous.
2. update Vivado version from 2017.3 to 2018.2
3. write 1000 address and read only for 500
4. pulldown app_en for some clocks while changing from read to write command or from write to read command.
can anyone helps.
03-06-2019 10:31 PM
Did you make any modification with DDR4 IP? Can you have a try to run simulation on the IP example design to check the simulation enviroment/settings?
03-06-2019 10:48 PM - edited 03-06-2019 11:15 PM
here are my ip settings.
I didn't do much change in setting.
I have studied and run the simulation in example design and the result is right.
The scope and timing was checked with datasheet.
I have no idea what did I missed.
06-11-2019 08:22 AM
Hello @moritz_hsiao ,
Your app_interface traffic masters are not driving the traffic correctly. First I would check out the User Interface section of PG150 starting on page 122 of the latest version. Next take a look at the Command Path, Write Path, and Read Path sections. When you're going over these keep in mind all three of these paths are independent so if your traffic master is not driving things correctly then you'll issue write commands without write data, or write commands to the wrong address, or fill the write data FIFOs without write commands. Next generate the example design on the KCU105 and run through the example design simulation to view the transactions on the app_interface. From there you can create a test with a smaller and smaller amount of transactions until you can isolate the scenario where your app_interface master goes wrong.
06-11-2019 06:38 PM
Would you please tell me why you know my app_interface is not driving correctly
I have checked and checked the waveform in PG150 for latest version(2018, April 4, p131-135).
But I didn't find any wrong on it.
Would you please note me what I should notice first? Thanks.
06-11-2019 11:41 PM
Is your problem reproduced in simulation? Before these write/read operations (with problem), from the ILA, it seems there's some other write/read transaction after DDR4 controller calibration. Right?
06-12-2019 06:38 PM
1. I ran the example desgin simulation before, the result is okay.
I have checked the timing and the waveform between example and mine.
There's no different.
2. The scope i attached is for 1000 write and 500 read inturn