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Observer bjackson_ost
Observer
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Registered: ‎03-12-2018

Clock sources on AXI side of DDR controller

I'm using the Memory Interface Generator to produce a DDR controller. I'm using UG586 (March 2, 2018) as a guide so I could configure what I need. I'm configuring for a DDR3 memory device and four AXI devices. On page 39 ("Memory Options for Controller 0 - DDR3 SDRAM" window), I need 4 clocks for the 4 devices I just mentioned. But that section to select additional clocks don't appear on my window. I need this for my design. Does anyone have any direction/suggestions for me so I could move forward?

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Moderator
Moderator
338 Views
Registered: ‎02-11-2014

Re: Clock sources on AXI side of DDR controller

Hello @bjackson_ost,

 

This question was recently asked and answered here: https://forums.xilinx.com/t5/Memory-Interfaces/clock-out-setting-in-mig-7-series-and-routing-error/m-p/842613/highlight/true#M11683

 

You need to be using IP Integrator with 7-Series MIG in order to get 4 additional clocks generated.

 

Thanks,
Cory

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