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Explorer
Explorer
293 Views
Registered: ‎11-23-2013

Create generated clock make a MIG error about IDELAYCTRL

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  1. I'm using Vivado 20017.4. In my project, I created a 200MHz clock by using a MMCM as below.
  2. IBUFG ibufg_i( .I(clk_src), .O(clk_src_int) );
  3. FreeRunningClkGen FreeRunningClkGen_i
    (
    .clk_out1(clk_10m), // output clk_out1
    .clk_out2(clk_200m), //
    .clk_out3(clk_250m),
    .clk_out4(clk_50m),
    .reset(rst), // input reset
    .locked(locked), // output locked

  4. .clk_in1(clk_src_int)); // input clk_in1, a 100MHz clock source

I didn't use a BUFG for the 'clk_in1' pin. The output clock 'clk_200m' is fed to a BUFG and used as ref clock for a ddr3 MIG. The project using this architecture was implemented successfully.

 

Then I add a new constrain:

create_generated_clock -name clk200m -source [get_pins -hierarchical -regexp {.*/FreeRunningClkGen_i/clk_in1}] -multiply_by 2 [get_pins -hierarchical -regexp {.*/FreeRunningClkGen_i/clk_out2}]

After this constraint applied to my project, an error appears during implementation. The error message is:小Q截图-20190124205210.png

   I don't know how the error happen? What does the 'create_generated_clock' constraint have done?

 

 

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1 Solution

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Moderator
Moderator
214 Views
Registered: ‎11-28-2016

Re: Create generated clock make a MIG error about IDELAYCTRL

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Hello @carnby,

From what I can tell the new constraint broke something and the IP no longer sees a 200MHz reference clock for the IDELAYCTRL.  I would take a closer look at the syntax for your command and the expected use cases and behaviors with the create_generated_clock command.  Take a look at this AR:
https://www.xilinx.com/support/answers/69583.html

3 Replies
Moderator
Moderator
215 Views
Registered: ‎11-28-2016

Re: Create generated clock make a MIG error about IDELAYCTRL

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Hello @carnby,

From what I can tell the new constraint broke something and the IP no longer sees a 200MHz reference clock for the IDELAYCTRL.  I would take a closer look at the syntax for your command and the expected use cases and behaviors with the create_generated_clock command.  Take a look at this AR:
https://www.xilinx.com/support/answers/69583.html

Explorer
Explorer
192 Views
Registered: ‎11-23-2013

Re: Create generated clock make a MIG error about IDELAYCTRL

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The MIG initiates 2 IDELAYCTRLs when the cycle time is less or equal than 1500ps, and the IDELAYCTRL which using 200MHz clock as ref clock will be removed during syth or impl.

In my project, the cycle time is 1500ps. So I guess the generated clock constraint prevents the Vivado from removing the unused IDELAYCTRL.

Finally, thanks for your reply. The ARs about 'create_clock' and 'create_genenrated_clock' are very helpful.

Explorer
Explorer
116 Views
Registered: ‎11-23-2013

Re: Create generated clock make a MIG error about IDELAYCTRL

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I think I have made a mistake.

When the cycle time of a MIG is less or equal than 1500ps, the IDELAYCTRL will use a 400MHz clock as refference clock. Alse the MIG will use 200MHz clock as XADC controlling clock. The 200MHz clock will not be synthsized away, it just hasn't IODELAY elements attatched to itself.

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