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Observer xinyiz
Observer
392 Views
Registered: ‎09-17-2018

DDR configuration

Hi, we are using Micron's LPDDR4(MT53E256M32D2DS-053AUT) in our MPSoC design. But I have issues on how to set the parameters in DDR configuration when customizing the MPSoC IP. Some parameters are not clearly specified in Micron's datasheet. Can you give me any suggestions? 

I put the Micron's datasheet attached.

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2 Replies
Observer xinyiz
Observer
379 Views
Registered: ‎09-17-2018

Re: DDR configuration

One supplement: There is not even a speed bin meeting the requirement of our chosen device.

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Xilinx Employee
Xilinx Employee
28 Views
Registered: ‎02-21-2019

Re: DDR configuration

Hello @xinyiz 

I am assuming that you're using a standard package type that allows for the higher data rates. If you're using a different package then the same logical flow applies for calculating your timing parameters based on a lower clock rate.  

Based on DS925 for Zynq UltraScale+ MPSOC, for a dual die package LPDDR4, the max data rate is 2133Mbps as shown in the screenshot below.  

3.png

For device frequency of 1066 MHz and a 8GB dual die LPDDR4, the following are the configuration settings per the Micron Data sheet:  

4.png

The DRAM density per channel is doubled since these are 16 bit channels giving us 8192Mbits per configuration in the Micron Data sheet as shown below:  

2.pngAs derived from above, here are the recommended settings:   

5.png

Here is the link to the supporting document for your reference:  

Zynq UltraScale + MPSOC - DS925 

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