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DDR2 SDRAM MIG - connect an ILA for debug purpose

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Visitor
Posts: 7
Registered: ‎06-12-2018
Accepted Solution

DDR2 SDRAM MIG - connect an ILA for debug purpose

Hi,

 

I am trying to generate a memory interface for DDR2 SDRAM present in Nexys DDR4. I have gone through the documentation and written the controller. Now I want to connect an ILA to be able to debug any issues. This is the basic code I have written for the controller - 

 

module top(
input clk_p,
input clk_n,
input rst,
inout [7:0] ddr2_dq,
inout [0:0] ddr2_dqs_n,
inout [0:0] ddr2_dqs_p,
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [0:0] ddr2_odt,
//output [63:0] app_rd_data,
output rd_out,
output app_rd_data_end,
output app_rd_data_valid
);

 

 

######### INSTANTIATION of mig_7series_0 with sys_clk_p/n connected to clk_p/n and ui_clk connected to ui_clk#########

 

###### INSTANTIATION of controller (this module is trigged by ui_clk and generates app* signals using app*rdy* signals ##### 

 

################# INSTANTIATION of ILA with some signal probes and the clk connected to clk_p####################

 

 

Is my clock connection correct?

I get the following error when I instantiate the ILA - 

[Opt 31-305] Invalid connectivity on net clk_p connected to port clk_p. It drives some loads that need a buffer, and other loads that do not need a buffer. This configuration cannot be placed.

How can I fix this?

 

 

I read somewhere that we can connect clk of ILA to the clock after IBUF of  sys_clk. But I dont know how to do that as the IBUF is inside the IP.

 

 


Accepted Solutions
Posts: 270
Registered: ‎02-11-2014

Re: DDR2 SDRAM MIG - connect an ILA for debug purpose

Hello @chirag.agrawal.91,

 

You should be able to turn on debug signals within MIG IP to debug calibration failure. If you are just looking to add signals to an ILA, and it's not working, you can always build MIG with sys_clk using "no buffer" which will take the IBUF outside of the IP, but then you are required to drive the logic. Our IP Example Design manually instantiates the IBUF for you in the top level wrapper with the "no buffer" option so this should give you what you want.

 

Let me know if this doesn't help.

 

Thanks,

Cory

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All Replies
Posts: 270
Registered: ‎02-11-2014

Re: DDR2 SDRAM MIG - connect an ILA for debug purpose

Hello @chirag.agrawal.91,

 

You should be able to turn on debug signals within MIG IP to debug calibration failure. If you are just looking to add signals to an ILA, and it's not working, you can always build MIG with sys_clk using "no buffer" which will take the IBUF outside of the IP, but then you are required to drive the logic. Our IP Example Design manually instantiates the IBUF for you in the top level wrapper with the "no buffer" option so this should give you what you want.

 

Let me know if this doesn't help.

 

Thanks,

Cory

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Visitor
Posts: 7
Registered: ‎06-12-2018

Re: DDR2 SDRAM MIG - connect an ILA for debug purpose

Hi Cory,

 

I agree that generating the IP without IO buffer would resolve my issue. How do I do that? I could not find that option anywhere in MIG. Also, after doing that will I have to manually instantiate an IBUF at top level?

Visitor
Posts: 7
Registered: ‎06-12-2018

Re: DDR2 SDRAM MIG - connect an ILA for debug purpose

Sorry I found it. It was along with the options "Differential and single ended". Thanks!
Visitor
Posts: 7
Registered: ‎06-12-2018

Re: DDR2 SDRAM MIG - connect an ILA for debug purpose

[ Edited ]

Hi  @coryb

 

I tried generating the MIG with sys_clock with no buffer. Now, i am facing a new issue. I get a synthesis warning on the ILA saying that all its outputs are unconnected and it is dropped. 

I don't see how the outputs are unconnected. Is there something I am missing?

 

Thanks,

Chirag