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Explorer
Explorer
1,013 Views
Registered: ‎05-14-2017

DDR3 IP, mig_7seriess:4.0. during read

Is there a bug with the DDR3 IP, mig_7seriess:4.0.

I send in 4 app_en during app_rdy=H with a read command to the memory controller interface and most of the time I get back 4 app_rd_data_valid=H.

But sometime I only get back 3

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20 Replies
Explorer
Explorer
982 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

I ran a continuous loop where I keep reading the same 4 address in DDR3 memory.

My sequence is to send 4 app_en when app_rdy=H then wait for 4 app_rd_data_valid then repeat this sequence.

 

after a while ( a few second) the memory controller doesn't return any app_rd_data_valid signal

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Moderator
Moderator
969 Views
Registered: ‎02-11-2014

Re: DDR3 IP, mig_7seriess:4.0. during read

Hello @tchin123,

 

Please upload your waveform so it can be analyzed.

 

Thanks,

Cory

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Explorer
Explorer
966 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

I found the issue, it was subtle but since the refresh occur so often, even though the rdy=h it drop the same time which coincide with my en=H

Explorer
Explorer
957 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

How often does XiIlinx memory controller DDR3 refreshes because I noticed that APP_RDY occur very often periodically.

I assume this is because it is refreshing the memory. It was measured (ILA) at 977 ns.

 

Is this the refresh rate at 977 ns. This is very fast. I thought it is normally it is 7.8 us?

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Moderator
Moderator
950 Views
Registered: ‎02-11-2014

Re: DDR3 IP, mig_7seriess:4.0. during read

Hello @tchin123,

There are only a few reason we de-assert APP_RDY as found in PG150:

app_rdy_low.PNG

Thanks,

Cory

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Explorer
Explorer
940 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

The app_rdy from the ddr3 memory controller is pulsing continuously at a period of 997 ns when there is no user activity.

pulse is 15 ns low.

Since I'm not generating any request this pulsing should come from the memory controller during refresh mode. Where else could cause this? It is very frequent.

 

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Moderator
Moderator
938 Views
Registered: ‎02-11-2014

Re: DDR3 IP, mig_7seriess:4.0. during read

Hello @tchin123,

Please provide your waveform so we can look into this issue.

Thanks,

Cory

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Explorer
Explorer
923 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

Attached is waveform file.

Top is full view and bottom is zoom within a period of app_rdy which is 977 ns.

When there is no user request the app_rdy remains the same

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Explorer
Explorer
908 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

here it is. I have to remove the wdb extension otherwise it complains

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Explorer
Explorer
892 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

i have to send in public message screen the private one doesn't have what you circle.

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Explorer
Explorer
885 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

Here is the ILA file.

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Explorer
Explorer
884 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

if you think a simulation file is better

It will take an hour, I will do it tomorrow, let me know

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Explorer
Explorer
853 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

Hi, based on the request and what I send to you, any idea why the interface ddr signal app_rdy pulses so frequent?

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Moderator
Moderator
724 Views
Registered: ‎02-11-2014

Re: DDR3 IP, mig_7seriess:4.0. during read

Hello @tchin123,

I have looked at your ILA data. As I thought, there is not enough information included to understand why the reset is triggering to often. A simulation will be the only way to understand the problem as I will be able to traverse throughout more transactions. There is something in your traffic pattern that is causing this issue, but I can't tell from the original waveform or this ILA capture. Make sure that you log ALL signals in your next simulation before uploading it.

Thanks,
Cory

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Explorer
Explorer
720 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

What signal do you need.

 

The only signal that affects the MIG IP controller APP_RDY are the

APP_EN, , APPCMD, APP_ADDR,

APP_WDF_WREN, APP_WDF_END, APP_WDF_RDY

From my hardcopy waveform, it shows all that.

There aren't any signal that could affects the APP_RDY from pulsing so often.

The other side on the controller go directly to SODIMM which is the MT8KTF51264HZ

 

 

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Moderator
Moderator
706 Views
Registered: ‎02-11-2014

Re: DDR3 IP, mig_7seriess:4.0. during read

Hello @tchin123,

You are correct. Those are the signals I need to analyze. The waveform you sent doesn't have these signals logged at the u2 level (which is the ddr3 controller) or at the u8_ddr3 level. I have traversed all through your hierarchy and do not see data. Are you sure you logged your simulation properly? If you could please "Log All Signals" during simulation and send that WBD, then we can continue debug.

Thanks,
Cory

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Explorer
Explorer
704 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

Strange, when I open the WDB file, I also do not see all the waveform.

I did a save before I generate this wdb file.

actually when I read this into vivado, it doesn't even shows the waveform window. it only show the object window. I never use this file before therefore i could have miss a step or two when saving and opening it.

All I did was a save then an open

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Explorer
Explorer
495 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

Attached is the ILA save result . this shows all activity with SODIMM from ddr3 controller.

 

The rdy signal is occurring very fast as mentioned

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Explorer
Explorer
494 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

its seem like i cannot attached a ILA file.

I change it to txt and still it couldn't be send

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Explorer
Explorer
336 Views
Registered: ‎05-14-2017

Re: DDR3 IP, mig_7seriess:4.0. during read

Finally here is the ILA file that shows the DDR3 fast cycle on the RDY signals.

The timing is between the fpga and the 4GB sodimm memory

As discussed it occurs too fast

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