Is there a bug with the DDR3 IP, mig_7seriess:4.0.
I send in 4 app_en during app_rdy=H with a read command to the memory controller interface and most of the time I get back 4 app_rd_data_valid=H.
But sometime I only get back 3
I ran a continuous loop where I keep reading the same 4 address in DDR3 memory.
My sequence is to send 4 app_en when app_rdy=H then wait for 4 app_rd_data_valid then repeat this sequence.
after a while ( a few second) the memory controller doesn't return any app_rd_data_valid signal
Please upload your waveform so it can be analyzed.
I found the issue, it was subtle but since the refresh occur so often, even though the rdy=h it drop the same time which coincide with my en=H
How often does XiIlinx memory controller DDR3 refreshes because I noticed that APP_RDY occur very often periodically.
I assume this is because it is refreshing the memory. It was measured (ILA) at 977 ns.
Is this the refresh rate at 977 ns. This is very fast. I thought it is normally it is 7.8 us?
There are only a few reason we de-assert APP_RDY as found in PG150:
The app_rdy from the ddr3 memory controller is pulsing continuously at a period of 997 ns when there is no user activity.
pulse is 15 ns low.
Since I'm not generating any request this pulsing should come from the memory controller during refresh mode. Where else could cause this? It is very frequent.
Please provide your waveform so we can look into this issue.
Attached is waveform file.
Top is full view and bottom is zoom within a period of app_rdy which is 977 ns.
When there is no user request the app_rdy remains the same