12-19-2018 06:36 AM
couple of issues with the DDR3 example project:
1. Vivado 2018.2 has the option to select PHY ONLY implementation grayed out while it is available on earlier versions of Vivado
2. Persistent 12-507 warning along with 'net not connected' error while trying to modify .XDC connect_debug_port clock net on the ILA debugger section when modifying per AR#64764
3. Instantiating differential clock buffer results implementation error constraints 18-608, cannot route within site IOB_X1Y80, conflicting nets for physical connection.
01-29-2019 09:58 AM
You cannot create a PHY ONLY implementation if the AXI4 Interface option is selected.
The next two errors seem related. You'll get 12-507 if you try to modify the constraint to something that isn't a physical net in the design.
The 18-608 is telling me there's a conflict between the IP constraints and your user constraints, or you're trying to move something that's already LOC'd by the IP.
01-29-2019 11:21 AM
01-29-2019 12:43 PM - edited 01-29-2019 12:44 PM
I did a quick test with 2018.2 and 2017.2 with the DDR3 IP.
When you add the IP from the catalog you can select Physical Layer Only option in both versions.
When you create a Block Design in IPI and add the DDR3 IP it defaults to enabling the AXI Interface so you can only select Controller and Physical Layer in both versions.
So both versions behaved the same.
As I pointed out before your original screenshot showed that the AXI Interface was enabled so you will not be able to generate a PHY Only option.