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Observer anilsutej
Observer
154 Views
Registered: ‎01-07-2012

DDR3 REFERENCE CLOCK GENERATION Issues Folllwing AR# 43876

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Hello,

We are using a 1Gb DDR3L Memory from Micron. MT41K64M16XX

Gone through Answer Record 

https://www.xilinx.com/support/answers/43876.html

But the suggested points are not helping. Here is the Ananlysis

1. Cannot Use " Use Sytem Clock" option because there is option to select in put frequency as 200MHz Clock

image.png

2. If we want to edit the Infrasturcture.v file 

 Generation of 200MHz is not possible with the steps described as the Memory Clock is defined as 333.333 MHz for optimum Performance.

If i slect 400MHz memory clock option then it is possible to generate 200MHz Reference clock as described

but there is Caution displayed as shown below 

image.png

So we wanted to keep the Memory clock as it is i.e 3000ps (333.333MHz) So,

what should be range of Reference Clock ? As we cannot generate 200MHz for sure with the Same PLL .

image.png

 

 

If we want to use UI_CLK(1/2 of Phy CLock = 166.667MHz In this Case) to generate REF_CLK(2000MHz in this Case) then we are facing a CLOCK_DEDICATED_ROUTE Issue as it is placing Modules in different blocks

Please suggest 

 

--Anil Sute

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Xilinx Employee
Xilinx Employee
106 Views
Registered: ‎08-21-2007

回复: DDR3 REFERENCE CLOCK GENERATION Issues Folllwing AR# 43876

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Please use the system input clock to generated the 200MHz and reset DDR3 IP after the system input clock get stable.

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Xilinx Employee
Xilinx Employee
130 Views
Registered: ‎08-21-2007

回复: DDR3 REFERENCE CLOCK GENERATION Issues Folllwing AR# 43876

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In AR#43876 case #1, the system input clock is 200MHz and reference clock is generated by the MMCM in MIG IP from this system input clock. 

In your system the DDR3 interfance is running 333MHz and system input clock is 400MHz?

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Observer anilsutej
Observer
110 Views
Registered: ‎01-07-2012

回复: DDR3 REFERENCE CLOCK GENERATION Issues Folllwing AR# 43876

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Hi Kren,

system input clock is 250MHz.

But i could resolve the issue by using another PLL to  genertae the 200MHz clock using 166.667MHz "UI_CLK".

But with extra Clock mocule i will have anothe 100mw more power. So i would like avoid it 

 

Thanks

Anil Sutej 

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Xilinx Employee
Xilinx Employee
107 Views
Registered: ‎08-21-2007

回复: DDR3 REFERENCE CLOCK GENERATION Issues Folllwing AR# 43876

Jump to solution

Please use the system input clock to generated the 200MHz and reset DDR3 IP after the system input clock get stable.

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