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Visitor paulcarson
Visitor
318 Views
Registered: ‎04-22-2014

DDR3 pin swapping on Artix7 (XC7A75T) and DDR3 (M41K128M16)

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Hi,

I'm at layout and the layout person has asked if I can change around DDR pins to make routing easier.

Originally I had tried using the MIG to auto-assign pins but it wouldn't let me assign them all to one bank.
So I have reused an existing design which already had the pins assigned on a single bank, so I used this to lower risk of problems later.

All the DRAM pins are on a single Bank 34, can I simply swap them around as requested on the FPGA end?

I looked at other forum posts and think I can but saw a comment that worried me "Provided, of course, that you are using a type of memory that allows pin swapping, e.g. DDR3.".

I only want to reassign the pins on the FPGa and not the DDR (if that's even possible).

Thanks,Paul

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Moderator
Moderator
280 Views
Registered: ‎11-28-2016

Re: DDR3 pin swapping on Artix7 (XC7A75T) and DDR3 (M41K128M16)

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Hello @paulcarson,

All MIG pinouts need to be validated by the tools to make sure they're following the Bank and Pin Selection Guides for DDR3 Designs starting on page 193 of the latest version (a link is in my signature).  Here since you already have a valid pinout, which I'm assuming is an XDC or UCF format, I would import it in to the tools when you get to the IO Planning Options page and select the "Fixed Pin Out" option.  There you can import the file and it will set all the pins, after that you can modify as you like, assuming the modifications you're trying to make are valid.  When you press "Validate" it will tell you if there were any errors.

6 Replies
Moderator
Moderator
281 Views
Registered: ‎11-28-2016

Re: DDR3 pin swapping on Artix7 (XC7A75T) and DDR3 (M41K128M16)

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Hello @paulcarson,

All MIG pinouts need to be validated by the tools to make sure they're following the Bank and Pin Selection Guides for DDR3 Designs starting on page 193 of the latest version (a link is in my signature).  Here since you already have a valid pinout, which I'm assuming is an XDC or UCF format, I would import it in to the tools when you get to the IO Planning Options page and select the "Fixed Pin Out" option.  There you can import the file and it will set all the pins, after that you can modify as you like, assuming the modifications you're trying to make are valid.  When you press "Validate" it will tell you if there were any errors.

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Voyager
Voyager
270 Views
Registered: ‎02-01-2013

Re: DDR3 pin swapping on Artix7 (XC7A75T) and DDR3 (M41K128M16)

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Ordinarily, the engineer sitting with the layout guy knows the pin swapping rules beforehand, would ok swaps on the fly, then go back and confirm the swaps using the FPGA design tool at the end of the day.

I'm not comfortable with the fact that the MIG wizard would't let you place the whole DDR interface in one bank, yet you found a way around that situation. So I also recommend that you use the MIG wizard to confirm your initial pin placement, before proceeding. Then look-up the pin swapping rules for DDR3 in 7 Series FPGAs, and bring them with you so you can approve further changes as they're made during layout.

-Joe G.

 

Visitor paulcarson
Visitor
249 Views
Registered: ‎04-22-2014

Re: DDR3 pin swapping on Artix7 (XC7A75T) and DDR3 (M41K128M16)

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Hi Joe @jg_bds,

thanks, I believe the design I copied actually copied the eval PCB and I did use the Validate function in the MIG. The design does implement so I'm confident it will work as is.

I'm just getting time now to follow Ryana's advise about Page 193 of UG586 so hopefully that'll answer my query and then I can confidently alter the pinout.

Hopefully I'll find out why the MIG tried to spread it across 2 banks!

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Visitor paulcarson
Visitor
243 Views
Registered: ‎04-22-2014

Re: DDR3 pin swapping on Artix7 (XC7A75T) and DDR3 (M41K128M16)

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Hi @ryana

thanks, I've been reading ug583 p.193 and believe I can swap pins safely using the Validate method in the MIG.

However reading this detail has alerted me to another issue with my design. As I've said my DDR is on Bank 34 but I put my 80MHz oscillator into Bank 15 for voltage rail reasons. Am I correct in concluding this is an error and I should move it to Bank 35 so that it will be in the same column and avoid jitter issues?

The 80MHz input drives a PLL to generate the 200MHz conencted directly to the UI clock input (sys_clk_i) and also reference clock (clk_ref_i). Perhaps I can keep the 80MHz pinned to Bank 15 and fix the PLL into Bank 34 ( I think this is possible)?

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Moderator
Moderator
227 Views
Registered: ‎11-28-2016

Re: DDR3 pin swapping on Artix7 (XC7A75T) and DDR3 (M41K128M16)

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Hello @paulcarson,

The recommendation is to have your clock enter in a bank within the same I/O column as the memory interface and, while the documentation doesn't explicitly disallow this, but I wouldn't want to generate both your system clock and reference clock internally.  Generating your system clock from a PLL adds more jitter but probably not that big of a deal with an Atrix device because your interface rate won't be that high anyway.  If you can't move the clock source to the MIG I/O column then I would try to LOC the PLL to be in the same I/O column as the memory interface.  Keep in mind the MIG is going to use some PLLs in the area so you'll have to make sure you're both not trying to use the same ones.

Visitor paulcarson
Visitor
97 Views
Registered: ‎04-22-2014

Re: DDR3 pin swapping on Artix7 (XC7A75T) and DDR3 (M41K128M16)

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Hi @ryana,

I've learned today how to constraint the PLL to a block, in this case X1Y2. The MIG is in X1Y1 & input 80MHz X0Y2.

Sadly the design didn't implement:


[Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets GCLKs_inst/inst/clk_in1_clk_wiz_0] >

	GCLKs_inst/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X0Y128
	The loads are distributed to 1 user pblock constraints. In addition, there are 0 loads not in user pblock constraints.

	Displaying the first 1 loads for pblock constraint 1
	GCLKs_inst/inst/plle2_adv_inst (PLLE2_ADV.CLKIN1) is provisionally placed by clockplacer on PLLE2_ADV_X1Y2


	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_pll_bufg
	Status: PASS 
	Rule Description: A PLL driving a BUFG must be placed on the same half side (top/bottom) of the device
	 GCLKs_inst/inst/plle2_adv_inst (PLLE2_ADV.CLKFBOUT) is provisionally placed by clockplacer on PLLE2_ADV_X1Y2
	 and GCLKs_inst/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

I then changed my input structure by regenerating the PLL without the "Single End clock capable pin" and used a "Global Buffer" instead.

In my VHDL I also added a BUFG and this should route the 80MHz on the global clock backbone to keep jitter minimal.

The design now implemented successfully ;-)