03-26-2012 11:36 AM
We need to repeatedly read same data from ddr3 (sequential read, no write). A fifo is used to synchronize the app_rd_data to our user_rd_clk. We observed that: if we set the user_rd_clk to 120MHz, everything is fine; however if the user_rd_clk is set to lower frequencies, such as 24MHz, 36MHz, 48MHz, we can find sparse one or two-bit errors in the 256-bit app_rd_data. All timing constants are met.
Did anyone have the same experience? Any suggestions? Thanks a lot.
03-27-2012 05:34 AM - edited 03-27-2012 05:35 AM
Are you running the memory too slowly to permit required refresh? Or are you varying only the user clock and not the memory clcok?
-- Bob Elkind
04-03-2012 02:15 PM - edited 04-03-2012 05:43 PM
The errors were caught at the fifo input. We also monitored the full signal. It was not full when the error occured.
04-03-2012 05:10 PM
One more thing. The problem occurs only when the full project is running. If only the ddr is running, there is no error.
04-03-2012 05:19 PM
memory clock is 400MHz. Yes, we only vaired the user clock. The memory clock is fixed.
For Virtex-6 MIG-generated designs, varying the user clock (to the user interface port of the controller) is not supported. From UG406 Table 1-18:
This UI clock must be half of the DRAM clock.
Are you targeting a Virtex-6 device?
Have you tried using the standard user clock (1/2 x memory clock) ?
-- Bob Elkind
04-03-2012 05:39 PM - edited 04-03-2012 05:40 PM
The name I used might be misleading. For "user_rd_clock", I mean the fifo read clock. The MIG UI clock (also the fifo write clock) is fixed at 200MHz.