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Participant mobileblue
Participant
4,927 Views
Registered: ‎02-05-2009

DDR3 read problem

hi, folks:

 

We need to repeatedly read same data from ddr3 (sequential read, no write). A fifo is used to synchronize the app_rd_data to our user_rd_clk. We observed that: if we set the user_rd_clk to 120MHz, everything is fine; however if the user_rd_clk is set to lower frequencies, such as 24MHz, 36MHz, 48MHz, we can find sparse one or two-bit errors in the 256-bit app_rd_data. All timing constants are met. 

 

Did anyone have the same experience? Any suggestions? Thanks a lot.

 

M.B

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7 Replies
Teacher eteam00
Teacher
4,905 Views
Registered: ‎07-21-2009

Re: DDR3 read problem

Are you running the memory too slowly to permit required refresh?  Or are you varying only the user clock and not the memory clcok?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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Xilinx Employee
Xilinx Employee
4,884 Views
Registered: ‎08-21-2007

Re: DDR3 read problem

Did you check if the data FIFO is full?

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Participant mobileblue
Participant
4,861 Views
Registered: ‎02-05-2009

Re: DDR3 read problem

Thanks for the reply.

 

memory clock is 400MHz. Yes, we only vaired the user clock. The memory clock is fixed.

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Participant mobileblue
Participant
4,860 Views
Registered: ‎02-05-2009

Re: DDR3 read problem

The errors were caught at the fifo input. We also monitored the full signal. It was not full when the error occured.

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Participant mobileblue
Participant
4,854 Views
Registered: ‎02-05-2009

Re: DDR3 read problem

One more thing. The problem occurs only when the full project is running. If only the ddr is running, there is no error.

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Teacher eteam00
Teacher
4,853 Views
Registered: ‎07-21-2009

Re: DDR3 read problem

memory clock is 400MHz. Yes, we only vaired the user clock. The memory clock is fixed.

 

For Virtex-6 MIG-generated designs, varying the user clock (to the user interface port of the controller) is not supported.  From UG406 Table 1-18:

 

This UI clock must be half of the DRAM clock.

 

Are you targeting a Virtex-6 device?

Have you tried using the standard user clock (1/2 x memory clock) ?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant mobileblue
Participant
4,851 Views
Registered: ‎02-05-2009

Re: DDR3 read problem

The name I used might be misleading. For "user_rd_clock", I mean the fifo read clock. The MIG UI clock (also the fifo write clock) is fixed at 200MHz.

 

 

 

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