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Newbie clin684
Newbie
7,403 Views
Registered: ‎04-12-2015

DDR3 unexpected read/write result and DDR3 address question

Hi there,

 

I'm trying to get DDR3 interfacing to work on an Artix-7 evaluation board for my school project.

 

The Artix-7 evaluation board has a SODIMMs (MT8JTF12864HZ-1G6) of 1GB with a data width of 64 bits. It runs at a clock rate of 400 MHz, with 200 MHz PLL input clock, and a 100 MHz output clock which I used with my interface logic. I have attached the specs of the RAM the MIG 7 generated.

 

My test interface only does two simple write in sequence, at address 8 (x"4869") and 16 (x"ACE"), and then two simple read at the same locations. The result is then displayed on the LCD display come with the board. When I programmed this and ran it on the board, somehow the 1st data been read is x"0000" and the 2nd data been read id x"202". After I pressed reset and let it ran again, the first data become x"08CE" and the 2nd data become x"ACE". I have tried adding wait states between the write and the read and performing the read right after each write, but the result is never what I'm expecting. Does anyone what the problem is? I have also attached my sample code.

 

Another question I have is about the address the UI uses. It is a 28 bit address, with 3 bit for the bank, 15 bit for the row, and 10 bit for the columns. Each address is 64bit. So, total of 2^28 * 64 bits = 2^28 * 8 bytes = 2^18 * 8 KB = 2 ^ 8 * 2 ^ 3 MB = 2 ^ 1 GB = 2 GB? But, the ram is only 1GB. Does that mean, I can only use 2 bit for the bank and leave the other bit at '0' all the time?

 

Thanks for your generous help!

Cheng

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