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DDR4 MIG drops first two words during read

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Observer
Posts: 38
Registered: ‎06-27-2013
Accepted Solution

DDR4 MIG drops first two words during read

I've generated the DDR4 MIG 2.0 for an Ultrascale+ device in Vivado 2016.2, and I'm trying out a simple simulation in which I write to the Micron memory model and read back.  During the read, I can see all of the correct data coming in on the data bus (c0_ddr4_dq), which is 64 bits wide in my case.  But when I look at what comes out of the user interface on the back side of the MIG, the first two 64-bit words are missing, and everything following is therefore misaligned.  I can repeatedly read the same location and get the same erroneous results.

 

The example design doesn't seem to have this issue when I simulate it in Vivado, but I'm at a loss for what the difference is between that simulation and mine (apart from the fact that I'm using QuestaSim).  I am using the same simulation model for the memory device.  I double-checked that my clock frequency is correct.


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Observer
Posts: 38
Registered: ‎06-27-2013

Re: DDR4 MIG drops first two words during read

The problem proved to be that I had the c0_ddr4_ck_c and c0_ddr4_ck_t signals swapped, i.e. connected to the wrong ports on the memory model interface.  You've got to connect c0_ddr4_ck_c to CK[0] and c0_ddr4_ck_t to CK[1], not the other way around.

 

Frankly I'm a little surprised that nothing *more* went wrong with an inverted clock between the MIG and the memory model, but happily it seems that correcting this has solved the missing read data problem.

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Moderator
Posts: 5,389
Registered: ‎09-20-2012

Re: DDR4 MIG drops first two words during read

Hi @jhane

 

Can you upload the waveform dump WLF/VCD showing the MIG user interface and PHY interface signals?

Thanks,
Deepika.
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Observer
Posts: 38
Registered: ‎06-27-2013

Re: DDR4 MIG drops first two words during read

Here's a VCD file for you to look at. Thanks for helping.

Highlighted
Observer
Posts: 38
Registered: ‎06-27-2013

Re: DDR4 MIG drops first two words during read

The problem proved to be that I had the c0_ddr4_ck_c and c0_ddr4_ck_t signals swapped, i.e. connected to the wrong ports on the memory model interface.  You've got to connect c0_ddr4_ck_c to CK[0] and c0_ddr4_ck_t to CK[1], not the other way around.

 

Frankly I'm a little surprised that nothing *more* went wrong with an inverted clock between the MIG and the memory model, but happily it seems that correcting this has solved the missing read data problem.