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Explorer
Explorer
925 Views
Registered: ‎01-23-2018

[DDR4 clock]

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Hi,

 

 

I have a confusion with the clocks that uses this block when it's created, and this questions will be so general but I need to be aware on what I'm doing.

 

I'm using VU9P -2 in package FLGB2014 and I have connected the ddr I/O pins to the fpga using the IO Planner. Once this pins are connected I understand that I don't have to do anything on constraints file (XDC) and all will work fine.

 

The DDR4 clock input is comming from sys_clk_p and sys_clk_n signals that are connected to the fpga pins. So there are my questions:

 

1) The frequency that this pins give to the module will be the reference input clock that I specified when I created it using the IP Catalog? Which one: "Memory Device Interface Speed" or "Reference Input Clock Speed"? And which clock speed I will receive on the user side? Because I need to use a dual-clock FIFO and I need that return value

 

 

Thanks

 

 

Regards,

 

Joel

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Moderator
Moderator
1,172 Views
Registered: ‎11-28-2016

Re: [DDR4 clock]

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Hello @joel.sanchez,

 

The clock frequency that you apply to the sys_clk_p/n pins is the "Reference Input Clock Speed."

 

The "Memory Device Interface Speed" is the DDR4 interface clock rate, and the user interface speed for the design is always 1:4 of the DDR4 interface rate. 

 

For example, if the Memory Device Interface Speed is set to 833ps, that means the DDR4 interface clock is 1200MHz, and then that means the user interface rate will be 300MHz.

 

Your "Reference Input Clock Speed" selection in the GUI is derived from the clocking requirements in the design, so you need to make sure that you're providing the correct "Reference Input Clock Speed" to your sys_clk_p/n pins when you configured the IP.

 

I encourage you to take a look at the example design and run a simulation for your configuration since that shows you how all of this works.

1 Reply
Moderator
Moderator
1,173 Views
Registered: ‎11-28-2016

Re: [DDR4 clock]

Jump to solution

Hello @joel.sanchez,

 

The clock frequency that you apply to the sys_clk_p/n pins is the "Reference Input Clock Speed."

 

The "Memory Device Interface Speed" is the DDR4 interface clock rate, and the user interface speed for the design is always 1:4 of the DDR4 interface rate. 

 

For example, if the Memory Device Interface Speed is set to 833ps, that means the DDR4 interface clock is 1200MHz, and then that means the user interface rate will be 300MHz.

 

Your "Reference Input Clock Speed" selection in the GUI is derived from the clocking requirements in the design, so you need to make sure that you're providing the correct "Reference Input Clock Speed" to your sys_clk_p/n pins when you configured the IP.

 

I encourage you to take a look at the example design and run a simulation for your configuration since that shows you how all of this works.