01-23-2019 01:41 AM
My FPGA board is VCU118. I want to integrate 16-bit DDR.
1. I generate .xci by Vivado 2017.4
2. I set constraint for DDR4 pin based on ug1224-vcu118-eval-bd.pdf.
The error appears in "Imeplementation" , "Opt Design". And the message is
[Mig 66-99] Memory Core Error -[u_ddr4_0] All the I/O Banks of the memory interface must be consecutive. (71,73) I/O Banks used for this interface are not consecutive.
I set pin constraint according to ug1224-vcu118-eval-bd.pdf. Why appers the error?
(Attached file is my constraint file)
01-23-2019 09:45 PM
My constraint file name is .sdc. I don't know why I can't attached fpga_constraint.sdc in this forum. So, I modify the filename into .docx. The original filename is fpga_constraint.sdc.
02-01-2019 10:02 AM
The reason you are seeing this error is because the memory IP expects the interface to be placed in consecutive I/O banks in the FPGA. Based on your description when you tried to use a x16 DDR interface you didn't select the DQ bits that were adjacent to the bank with the Command/Address/Control signals. Looking at the VCU118 example design Channel 1 is placed in banks 71-73 with the CAC bus placed in Bank 71. If you want to target a single x16 device then I would generate a design that uses DQS6 and DQS7 with their associated DQ bits since these are in Bank 72. You can try to use DQS0 and DQS9 that are in Bank 71 but those are routed to different memory devices, which is perfrectly fine for fly-by routing with this topology but if you're trying to make SI measurements this may be annoying. Based on your XDC you used DQS0 and DQS1, where DQS0 is in Bank 71 but DQS1 is in Bank 73, so that's why the tools complained.