UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor stagger
Visitor
4,334 Views
Registered: ‎01-17-2008

Design w/ multiple MIGs

I am working in Vivado 2015.4 with several variations of a design that uses four MIGs to control 4 separate banks of DDR3 memory.  I note that in the designs I have previously produced, in the Configuration Files folder in the Hierarchy tab, I would see two files named "mig_a.prj" and two named "mig_b.prj".  In my most recent project, however, I note 3 instances of mig_a.prj, and only one mig_b.

 

What is the purpose of these project files, and what differentiates a mig_a project from a mig_b project?  Can I expect one of the memory controllers to fail because it should be a "b", but has been designated as an "a"?

0 Kudos
2 Replies
Visitor stagger
Visitor
4,330 Views
Registered: ‎01-17-2008

Re: Design w/ multiple MIGs

BTW - the MIG version for the above project is Ver. 2.4, rev.1

0 Kudos
Xilinx Employee
Xilinx Employee
4,305 Views
Registered: ‎08-01-2008

Re: Design w/ multiple MIGs

If the MIG in the BD is multi-controller then there will be more than one mig_#.prj file
check this ARs
http://www.xilinx.com/support/answers/58852.html
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos