UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
473 Views
Registered: ‎11-08-2018

FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

Hello everyone,

I have 2 question(problem):

1: [Netlist 29-160] Cannot set property 'IOSTANDARD', because the property does not exist for objects of type 'pin'.

FIGURE 1 and 2

--->I have used 2 ports,Sys_clock_i and Clk_ref_i.When I using 2 ports from Mig7 but i can not connected in vivado because it is hide.I can not use it to connect to the ports.
2: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs: ddr3_sdram_ck_p[0] (DIFF_SSTL135, requiring VCCO=1.350) and reset (LVCMOS33, requiring VCCO=3.300)

FIGURE 3

-->I don't knowunderstand a clearly way.

If Anyone knows the answer please talk to me.

Thank you very much,

tuan,

figure1.PNG
figure2.PNG
figure3.PNG
0 Kudos
14 Replies
Voyager
Voyager
434 Views
Registered: ‎02-01-2013

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc


tuan94@ wrote:

Hello everyone,

I have 2 question(problem):

1: [Netlist 29-160] Cannot set property 'IOSTANDARD', because the property does not exist for objects of type 'pin'.

FIGURE 1 and 2

--->I have used 2 ports,Sys_clock_i and Clk_ref_i.When I using 2 ports from Mig7 but i can not connected in vivado because it is hide.I can not use it to connect to the ports.

     I encounter this error when I forget to connect a pin to a top-level IO. Vivado can find the signal name, but it's attached to an internal pin, not to an external IO pin. Either externalize the signal, or remove the IOSTANDARD and PACKAGE_PIN constraints for it.


2: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs: ddr3_sdram_ck_p[0] (DIFF_SSTL135, requiring VCCO=1.350) and reset (LVCMOS33, requiring VCCO=3.300)

FIGURE 3

-->I don't knowunderstand a clearly way.

     You set the IOSTANDARD for your reset pin to an inappropriate level. Either you set it to LVCMOS33 directly, or it was set by default. You can't have an LVCMOS33 signal in a bank that's powered by 1.35V. You should move that reset signal to another bank.

If that reset is your DDR reset...Uh-oh. The DDR reset signal needs to meet LVCMOS levels. Unfortunately, there's no LVCMOS135. Your best bet would be to move the DDR reset to a different bank (powered by 1.5V, preferably) and drive the signal with an open-drain output that has an external pull-up to the 1.35V you're using to power the DDR(3L).

If Anyone knows the answer please talk to me.

Thank you very much,

tuan,


 

Adventurer
Adventurer
422 Views
Registered: ‎11-08-2018

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

Hi jb_bds,

Thank your answer,

Question 1:Can you show me how to remove IOSTANDARD and PACKAGE_PIN so what it mean.
If I change so what's happen with my program.
Question 2:In Mig7,Can I change the value from 1,35V to 1,5V?Right?
Before,I was changed the reset Ports to the diference Bank but It appears the diference ports.(Sys clock,Led 4 bit Tri,Rgb Tri ......)
And when i get all it out,it appears error.


Have a nice day,

tuan,

0 Kudos
Voyager
Voyager
414 Views
Registered: ‎02-01-2013

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc


tuan94@ wrote:

Hi jb_bds,

Thank your answer,

Question 1:Can you show me how to remove IOSTANDARD and PACKAGE_PIN so what it mean.
If I change so what's happen with my program.

You originally presented questions about critical warnings and an error. I tried to explain them for you. Overall, I don't know what you're trying to do--only you know that. I can tell you how to do what you ask, but if you don't know what will happen as a result, maybe you should go back and figure out why you're doing this.


Question 2:In Mig7,Can I change the value from 1,35V to 1,5V?Right?
Before,I was changed the reset Ports to the diference Bank but It appears the diference ports.(Sys clock,Led 4 bit Tri,Rgb Tri ......)
And when i get all it out,it appears error.

I don't know. Once again: I don't know what you're doing--only you do, unless you tell me.

It's possible to run DDR3L at 1.5V. Running it at 1.5V could be an easier path for you. If the signal you're dealing with (the one that caused the error) is the DDR reset signal (and I don't know that it is, because you haven't told me what it is...) you'll be able to drive it with LVCMOS15.


Have a nice day,

tuan,


 

Adventurer
Adventurer
408 Views
Registered: ‎11-08-2018

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

Hi , 

About

Question 1:I don't know that error and how to fix.You said me " You should change IOSTANDAN or PACKEGE_PIN".I want ask you how to change.?

Question 2: i don't know your mean about reset use for IOSTANDAND or reset use for DDR3L

it is the same reference(IOSTANDAND ) and system(DDR3L) ports

I want to fix errors @jg_bds

Thank you very much,

tuan,

 

0 Kudos
Voyager
Voyager
390 Views
Registered: ‎02-01-2013

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc


tuan94@ wrote:

Hi , 

About

Question 1:I don't know that error and how to fix.You said me " You should change IOSTANDAN or PACKEGE_PIN".I want ask you how to change.?

No, I said "remove the IOSTANDARD and PACKAGE_PIN constraints". You can do that by going into the file that contains those constraints and commenting out lines 263, 264, 267 and 268. You comment-out a line by putting a "#" at the beginning of it. Keep in mind, the tool is reporting these issues as Critical Warnings, not Errors.

2019-01-30_22-56-37.jpg

Question 2: i don't know your mean about reset use for IOSTANDAND or reset use for DDR3L

it is the same reference(IOSTANDAND ) and system(DDR3L) ports

Open your synthesized design.  Find the reset signal in the I/O Ports tab at the bottom of the screen.

2019-01-30_23-07-59.jpg

Change the I/O Std column for that signal from LVCMOS33 to SSTL135. Save the design before you close it.

 

I want to fix errors @jg_bds

Thank you very much,

tuan,

 


 

Adventurer
Adventurer
374 Views
Registered: ‎11-08-2018

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

Hi,

Actually,i thank you very much because you were answers me.

About:

Question 1:I know your remove way.I will perform.
Figure 1.This is a way I get 2 ports(Sys_clk,Clk_ref).I am not sure but i think Single(Reference) and Nubuffer(System)
Question 2:I know and I have performed before.But when I fix all errors.ERROR

figure33.PNG
figure11.PNG
figure22.PNG
0 Kudos
Voyager
Voyager
311 Views
Registered: ‎02-01-2013

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

 

Are you working with a standard Xilinx (or other) reference board design, or a is this a custom board that you've built.?

-Joe G.

 

0 Kudos
Adventurer
Adventurer
167 Views
Registered: ‎11-08-2018

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

Hi Joe,

I am Sorry because I was lated,I having a problem.

That is a a standard Xilinx reference board design,but I have changed something.
This is a project and I am a part in That project.My job is design block.
We want to send Data from Microblaze to Mig7 thought A Block(we was designed,it is called : Hispeed )

When I design block,i see some error and I was fixed it.Now I don't understand that "waring" ,

I have readed even MMCM and PLL,but i don't under it.I have searched on Web.Someone answer 

"Because You don't connect it with High Source"
I want to know. " Sys_clk_i and Clk_ref_i" .
So If you know the answer please tell me or give an ideal at anywhere.

Thank you so much,

Best wishes for you,

Happy New Year,

Tuan,

0 Kudos
Voyager
Voyager
158 Views
Registered: ‎02-01-2013

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

 

Did you do this yet?

2019-02-12_7-15-30.jpg

-Joe G.

 

0 Kudos
Adventurer
Adventurer
137 Views
Registered: ‎11-08-2018

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

Hi Joe,

I have do that.After I remove the value of Bank (Bank 35,Include: dram_....  SSTL 15 and Reset,Sysclock,rgb_tri_,led_4bit_tri with LMOS 33.I have removed to SSTL 15 and unbelievable it was success.
Just have 4 Waring.Because It is the waring, if I change or fix it so what is happend ? like what's affect,relative,....?
I am reading 

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
and
https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
Is it correctly?
When  you said me " remove it by # ", I was doing that,but I dont know what is going to happen ?


Thank you so much,

tuan, 

Capture.PNG
Capture1.PNG
0 Kudos
Voyager
Voyager
128 Views
Registered: ‎02-01-2013

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

 

Most of the time Warnings can be ignored. Critical Warnings, however, should be addressed and cleared-up.

-Joe G.

0 Kudos
Adventurer
Adventurer
116 Views
Registered: ‎11-08-2018

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

Hi Joe,

Thank you for answer,

That's I need.
Can you fix that?
Please give me an ideal or suggestion for me? and I can fix that.

Thank you so much,

tuan,

0 Kudos
Voyager
Voyager
92 Views
Registered: ‎02-01-2013

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

 

Look at the constraints on lines 263, 264, 267, and 268. See what they are. If the constraints aren't needed, remove them (again?) like we did earlier (above).

-Joe G.

 

0 Kudos
Adventurer
Adventurer
72 Views
Registered: ‎11-08-2018

Re: FPGA ARTIX 7 : Cannot set property IOSTANDARD and [DRC BIVC-1] Bank IO standard Vcc

Hi Joe,

Thank your answer,

I know that,the begin,I am setting Mig7 include Sys_clk_i and Clk_ref_i.Sys_clk_i with system_clock (166,667 Mhz),Clk_ref_i with clock(200,000Mhz). 
After I set " in Mig7 Block " and I am using Single_end,It has 3 mode (Single_end,No buffer,Different)
About your answer " If the constraints aren't needed ",If I remove them ( use # ) so In the System,
That port is used ??? 

=)))) One more thing,Do you know about Report Timing Summary.I have readed some Page but I dont understand a clearly way.

Best wishes for you,

tuan,

Capture11.PNG
Capture22.PNG
0 Kudos