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Explorer
Explorer
848 Views
Registered: ‎04-19-2016

HR banks maximum frequency for QDRII+ SRAM

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Hello,

 

What is the disadvantage of the using HR IO banks, instead of HP IO banks for a QDRII+ type SRAM interface ? Maybe there is an maximum frequency limit or maximum data rate for HR IO banks for a proper QDRII+ interface? 

 

All HP banks are used by DDR3, and there is no HP IO for QDRII+ .

 

Thank you.

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Moderator
Moderator
1,158 Views
Registered: ‎09-18-2014

Re: HR banks maximum frequency for QDRII+ SRAM

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Doner_t,

 

 

 

What is the disadvantage of the using HR IO banks, instead of HP IO banks for a QDRII+ type SRAM interface ? 

 

 

-A quick answer to your solution would lie in understanding the difference between HR and HP IO bank purposes. There is no "disadvantage" of using an HR IOs per say, I would put it as there are more "advantages" with the HP IOs as they support the features that enable higher performance like a dedicated VCCAUX_IO rail(can be run @2.0V for +performance), digitally controlled impedance(calibrated/tuned), low voltage operation and so on. 

 

 

Maybe there is an maximum frequency limit or maximum data rate for HR IO banks for a proper QDRII+ interface? 

 

-Yes, have you looked at the "PL Performance Characteristics" in your devices datasheet? I am assuming you are using a Zynq part given your other/previous posts so I've snapped a portion of table 53 from DS191 for your reference. You could also go the route Jmcclusk mentioned below and pop up the two implementations in Vivado MIG IP. It should match the datasheet figures in terms of the penalties/limitations. 

 

DDR perf specs.JPG

 

Regards,

T

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Scholar jmcclusk
Scholar
845 Views
Registered: ‎02-24-2014

Re: HR banks maximum frequency for QDRII+ SRAM

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You should be able to tell if there's a penalty by running the MIG tool, and generating sample designs for both type of banks.  It wouldn't be surprising if there's a speed penalty..  but the MIG tool will show you what it is.

Don't forget to close a thread when possible by accepting a post as a solution.
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Moderator
Moderator
1,159 Views
Registered: ‎09-18-2014

Re: HR banks maximum frequency for QDRII+ SRAM

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Doner_t,

 

 

 

What is the disadvantage of the using HR IO banks, instead of HP IO banks for a QDRII+ type SRAM interface ? 

 

 

-A quick answer to your solution would lie in understanding the difference between HR and HP IO bank purposes. There is no "disadvantage" of using an HR IOs per say, I would put it as there are more "advantages" with the HP IOs as they support the features that enable higher performance like a dedicated VCCAUX_IO rail(can be run @2.0V for +performance), digitally controlled impedance(calibrated/tuned), low voltage operation and so on. 

 

 

Maybe there is an maximum frequency limit or maximum data rate for HR IO banks for a proper QDRII+ interface? 

 

-Yes, have you looked at the "PL Performance Characteristics" in your devices datasheet? I am assuming you are using a Zynq part given your other/previous posts so I've snapped a portion of table 53 from DS191 for your reference. You could also go the route Jmcclusk mentioned below and pop up the two implementations in Vivado MIG IP. It should match the datasheet figures in terms of the penalties/limitations. 

 

DDR perf specs.JPG

 

Regards,

T

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