04-17-2019 10:06 AM - edited 04-17-2019 01:19 PM
I'm running post implementation functional simulation on the example desing for MIG DDR3 controller for Virtex Ultrascale and don't see the init_calib_complete signal go high.
I want to dump a SAIF file for power analysis, but that isn't working as required due to no activity for a very long time.
Can anyone tell me how long it would take with a 14ns input clock?
I read on some other thread that SIM_BYPASS_INIT_CAL = "SKIP" can be used to skip initialization but i dont't know where I can find this variable/enum or how to set it.
To add to this, it takes 5us for init_calib_complete to go high in behavioral simulation. The example test finishes with no errors.
I've run my post implementation for 1 ms with no success
I've attached log and simulation screenshots.
04-18-2019 07:28 AM
Thanks for your response. I'm concerned how I can get the power report for my desgn in that case. So if I dump SAIF from behavioral simulation, would the signals internal to the design (such as init_calib_complete) also switch according to the activation file or is it only the signals that are input to the design from outside ? Would the switching of external signals make the init_calib_complete go high, so that correct power report is obtained?