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Visitor pr1498
Visitor
233 Views
Registered: ‎03-04-2019

How long does it take for MIG DDR3 controller init_calib_complete to assert

Hi,

I'm running post implementation functional simulation on the example desing for MIG DDR3 controller for Virtex Ultrascale and don't see the init_calib_complete signal go high. 

I want to dump a SAIF file for power analysis, but that isn't working as required due to no activity for a very long time.

Can anyone tell me how long it would take with a 14ns input clock?

I read on some other thread that SIM_BYPASS_INIT_CAL = "SKIP" can be used to skip initialization but i dont't know where I can find this variable/enum or how to set it.

 To add to this, it takes 5us for init_calib_complete to go high in behavioral simulation. The example test finishes with no errors.
I've run my post implementation for 1 ms with no success

I've attached log and simulation screenshots.

Thanks,

Parul

 

post_imp_eg_design.png
post_imp_eg_sim.png
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3 Replies
Xilinx Employee
Xilinx Employee
176 Views
Registered: ‎08-21-2007

回复: How long does it take for MIG DDR3 controller init_calib_complete to assert

For MIG design, only behavirol simuation is supported. 

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Visitor pr1498
Visitor
165 Views
Registered: ‎03-04-2019

回复: How long does it take for MIG DDR3 controller init_calib_complete to assert

Hi Kren,

Thanks for your response. I'm concerned how I can get the power report for my desgn in that case. So if I dump SAIF from behavioral simulation, would the signals internal to the design (such as init_calib_complete) also switch according to the activation file or is it only the signals that are input to the design from outside ? Would the switching of external signals make the init_calib_complete go high, so that correct power report is obtained?

Thanks,

Parul

 

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Xilinx Employee
Xilinx Employee
115 Views
Registered: ‎08-21-2007

回复: How long does it take for MIG DDR3 controller init_calib_complete to assert

You can estimate the power from XPE spreasheet.

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