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Registered: ‎03-23-2015

How to package a project with a MIG core?



I am not sure if I should post this here or under the Vivado tool, hopefully if I am wrong a moderator can move it.


This thread is similar to my issue, however not the same, and I can't fix it replicating the solution: http://forums.xilinx.com/t5/Design-Entry/Packaged-IP-project-containing-MIG-fails-in-Vivado-2014-3/m-p/547629#M7146


The thing is I have a project with a MIG core. No Block-Design, there is the MIG XCI file with all of it's generated outputs and then basically I instanciated the example_design which comes with (in order to do some hardware validation tests), so my mig core is now a module within my top module called "example_top", where it is instanciated like any other verilog module.


This project works fine on it's own, generates outputs, synthesises, etc..


However I want to package this into a new IP in order to be able to instanciate it from another project's block design. Then my first question arouses, what am I supposed to do with the MIG PRJ file? As far as I can tell the XCI does not contain all the information (pinout among many others) and as far as I know the XCI file is actually generated from the PRJ file, so I package the MIG PRJ file (I have tried to put it under numerous file groups with no success) and package it.

Then, when I instanciate it and generate the output files I get this error:


[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3/xit/synthesis.xit':
[IP_Flow 19-3419] Update of 'DDR3_PL' to current project options has resulted in an incomplete parameterization. Please review the upgrade log '.../x.srcs/sources_1/bd/y_top/ip/y_top_ddr3b_bist_0_0/sources_1/ip/DDR3_PL/DDR3_PL.upgrade_log', and recustomize this instance before continuing with your design.


[xilinx.com:ip:mig_7series:2.3 0] DDR3_PL: Code generation aborted: Unconfigured MIG instance

[IP_Flow 19-167] Failed to deliver one or more file(s).

[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'DDR3_PL'. Failed to generate 'Synthesis' outputs:

[IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'DDR3_PL'. Failed to generate 'Synthesis' outputs:

[BD 41-1030] Generation failed for the IP Integrator block ddr3b_bist_0


The log files reads: 


Upgrade Log for IP 'DDR3_PL'

1. Summary

CAUTION (success, with warnings) in the update of DDR3_PL (xilinx.com:ip:mig_7series:2.3) to current project options.

After upgrade, an IP may have parameter differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality.

2. Customization warnings

WARNING: Validation failed on parameter 'XML_INPUT_FILE(XML_INPUT_FILE)' for Specified PRJ file does not exist 'mig_a.prj'
. IP 'DDR3_PL'

WARNING: Customization errors found on 'DDR3_PL'. Restoring to previous valid configuration.

3. Debug Commands

  The following debug information can be passed to Vivado as Tcl commands,
in order to validate or debug the output of the upgrade flow.
  Please consult the warnings from the previous sections, and alter or remove
the configuration parameter(s) which caused the warning; then execute the Tcl
commands, and use the IP Customization GUI to verify the IP configuration.

create_ip -vlnv xilinx.com:ip:mig_7series:2.3 -user_name DDR3_PL
set_property -dict "\
  CONFIG.Component_Name DDR3_PL \

for what I can see it says it did not find the PRJ file, however I have checked, and the PRJ file is in the same path as the XCI file and the XCI say's the following:


<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XML_INPUT_FILE">mig_a.prj</spirit:configurableElementValue>


What am I supposed to do? the truth is that this is the first time I package a xilinx's core and I am not even sure if I am supposed to include the XCI file (The only other way would be to include all the generated sources but I would really like to avoid that). If I am supposed to include it, under which fileset??


Any help will be welcomed.

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4 Replies
Registered: ‎03-23-2015

Re: How to package a project with a MIG core?

I think I was not clear enough, when I package the project I include both the XCI file and the PRJ file
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Registered: ‎03-23-2015

Re: How to package a project with a MIG core?

really?... nobody? :(


I found this thread which is pretty similar but I still can't get it to work.. i am not sure if I am doing something wrong when packaging an XCI file (Xilinx Ip) or if it is an specific MIG problem... http://forums.xilinx.com/t5/Design-Tools-Others/How-to-pack-a-user-design-with-Xilinx-IP-in-Vivao/m-p/492396#M6672


I still don't really know how is one supposed to pack an XCI file exactly.. like what file group should it appear under?

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Registered: ‎03-23-2015

Re: How to package a project with a MIG core?

Well I guess I am on my own... I tried this with no luck, even though it seems to describe my error pretty acurately.




I'm attaching my packaged IP in case someone can help me, the error appears when you instanciate this IP core into a project.

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Visitor syang
Registered: ‎04-11-2018

Re: How to package a project with a MIG core?

Hi arquer, did you ever figure this out? How do you associate the repackaged MIG core with the MIG GUI?

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