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Adventurer
Adventurer
10,699 Views
Registered: ‎08-08-2009

I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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I use ML507 Evaluation Platform ( XC5VFX70T ) . I use MIG v3.4 and ISE v12.1. Which ports can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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Xilinx Employee
Xilinx Employee
12,574 Views
Registered: ‎08-16-2007

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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I just took a look in the ML507 MIG reference design and see that design uses the following:

 

NET  "sys_clk_p"                                 LOC = "H14" ;      #Bank 3
NET  "sys_clk_n"                                 LOC = "H15" ;      #Bank 3
NET  "clk200_p"                                  LOC = "L19" ;      #Bank 3
NET  "clk200_n"                                  LOC = "K19" ;      #Bank 3
NET  "sys_rst_n"                                 LOC = "E9";      #Bank 20
NET  "phy_init_done"                             LOC = "H18" ;      #Bank 3

 

NET  "sys_clk_p"                                 LOC = "H14" ;      #Bank 3

NET  "sys_clk_n"                                 LOC = "H15" ;      #Bank 3

NET  "clk200_p"                                  LOC = "L19" ;      #Bank 3

NET  "clk200_n"                                  LOC = "K19" ;      #Bank 3

NET  "sys_rst_n"                                 LOC = "E9";      #Bank 20

NET  "phy_init_done"                             LOC = "H18" ;      #Bank 3

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Xilinx Employee
Xilinx Employee
12,575 Views
Registered: ‎08-16-2007

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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I just took a look in the ML507 MIG reference design and see that design uses the following:

 

NET  "sys_clk_p"                                 LOC = "H14" ;      #Bank 3
NET  "sys_clk_n"                                 LOC = "H15" ;      #Bank 3
NET  "clk200_p"                                  LOC = "L19" ;      #Bank 3
NET  "clk200_n"                                  LOC = "K19" ;      #Bank 3
NET  "sys_rst_n"                                 LOC = "E9";      #Bank 20
NET  "phy_init_done"                             LOC = "H18" ;      #Bank 3

 

NET  "sys_clk_p"                                 LOC = "H14" ;      #Bank 3

NET  "sys_clk_n"                                 LOC = "H15" ;      #Bank 3

NET  "clk200_p"                                  LOC = "L19" ;      #Bank 3

NET  "clk200_n"                                  LOC = "K19" ;      #Bank 3

NET  "sys_rst_n"                                 LOC = "E9";      #Bank 20

NET  "phy_init_done"                             LOC = "H18" ;      #Bank 3

Adventurer
Adventurer
10,688 Views
Registered: ‎08-08-2009

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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Thank you very much about your help !

But the MIG generate the I/O STANDARDS is:

NET  "sys_clk_p"                               IOSTANDARD = LVCMOS25;
NET  "sys_clk_n"                               IOSTANDARD = LVCMOS25;
NET  "clk200_p"                                 IOSTANDARD = LVCMOS25;
NET  "clk200_n"                                 IOSTANDARD = LVCMOS25;

NET  "sys_rst_n"                                IOSTANDARD = LVCMOS18;
NET  "phy_init_done"                        IOSTANDARD = LVCMOS18;

 

If I use your LOC,are these change to:

 

NET  "sys_clk_p"                               IOSTANDARD = LVPECL_25;
NET  "sys_clk_n"                               IOSTANDARD = LVPECL_25;
NET  "clk200_p"                                 IOSTANDARD = LVPECL_25;
NET  "clk200_n"                                 IOSTANDARD = LVPECL_25;
NET  "sys_rst_n"                                IOSTANDARD = LVCMOS33;                                   (  DCI  ?  )
NET  "phy_init_done"                        IOSTANDARD = LVCMOS25;

 

Is the sys_clk 266MHz?   :

 

NET  "sys_clk_n"         LOC="H15";   # Bank 3, Vcco=2.5V, No DCI     
NET  "sys_clk_p"         LOC="H14";   # Bank 3, Vcco=2.5V, No DCI  

 

Where do you find these detailed information about ML507 ?

Can you give me the links if those come from the www ?

 

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Teacher eteam00
Teacher
10,665 Views
Registered: ‎07-21-2009

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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The MIG-generated files are not completely 'golden'.  If corrections or changes need to be made, go ahead and make them.  Specifically, the IOSTANDARD parameters, for anything not tied directly to the DRAM, are your decision (not MIG).

 

In this case, for example, the UCF entries for the clock IOs must match your board design.

 

Bottom line:  MIG does not generate files which cannot be modified by the user.  In some respects, it is your obligation to modify the result files.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Xilinx Employee
Xilinx Employee
10,633 Views
Registered: ‎11-29-2009

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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Hi,

 

You can find ML507 documentation in below link.

 

http://www.xilinx.com/products/boards/ml507/docs.htm

 

The IOSTANDARDS are fixed and MIG generated UCF files follow the MIG guidelines and are tested well, and its advised not to modify any of the files generated by MIG tool. Since it may lead to other issues while implementing on the board.

 

Thanks

Highlighted
Teacher eteam00
Teacher
10,631 Views
Registered: ‎07-21-2009

user edits to MIG-generated files

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Using MIG3.5 (current latest version) with Spartan 6 target, I find that the MIG-generated files need some minor tweaks to fit my design.

 

Specifically:

  1. UCF file - VCCAUX defaults to 2.5V, my application is 3.3V

  2. UCF file - net c1_sys_clk is defined to LVCMOS25 IO standard, which is incorrect for my design

  3. UCF file - net c1_sys_rst_n is defined to LVCMOS18 IO standard, which is incorrect for my design

  4. file memc1_infrastructure.v must be customised to accommodate low-frequency source clock

  5. UCF file - all signal names are generated by MIG, and may not match your preferred pin/signal name preference

  6. Several files must be edited if you wish to use the 2 unused PLL outputs instantiated in memc1_infrastructure.v

 

These are examples (which may not apply to some designs or some target FPGA device families) for the need to edit or customise the files generated by MIG.  MIG is not (yet) clever enough to match your design target in all respects.

 

Of the items cited above, #4 and #6 have been submitted as part of a webcase which is currently open.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Adventurer
Adventurer
10,612 Views
Registered: ‎08-08-2009

Re: user edits to MIG-generated files

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Thank you for your detailed answer.

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Visitor xavier.gonon
Visitor
9,789 Views
Registered: ‎12-01-2010

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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Hi,

 

I'm really surprised to see the pinout you give for the DDR2 embedded on the ML507...

If you take a look at the Memory Interface Generator Design for the ML507 you have the following pinout in the file "mig_v3_4\user_design_par":

 

NET "sys_clk_p" LOC = "H17" ; #Bank 3

NET "sys_clk_n" LOC = "H18" ; #Bank 3

NET "clk200_p" LOC = "K17" ; #Bank 3

NET "clk200_n" LOC = "L18" ; #Bank 3

NET "sys_rst_n" LOC = "D32" ; #Bank 11

NET "phy_init_done" LOC = "C34" ; #Bank 11

 

 

Can anyone please help me putting things clear about the ML507 DDR2 pinout (actually differential clocks inputs).

Thanks

 

Xavier

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Teacher eteam00
Teacher
9,785 Views
Registered: ‎07-21-2009

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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What are your questions, xavier?

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor xavier.gonon
Visitor
9,739 Views
Registered: ‎12-01-2010

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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You're right, I should have been a bit more accurate writting my previous post....

 

My question is :

 

- Implementing a MIG controller on the ML507 dev board to use the DDR2 memory, without using the SMA cables, what is the apporopriate pinout to provide the Virtex-5 with the 200Mhz and the 266Mhz differentials clocks?

 

My guess is that we can get clk200_p at pin  L19 and clk200_n at pin K19, I don't know if it's right (UG347 page 20).

Now, I don't know where to get sys_clk_p and sys_clk_n (266Mhz) without using the SMA cables?

 

Thanks to help solve this issue.

 

Cheers.

 

Xavier

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Teacher eteam00
Teacher
6,517 Views
Registered: ‎07-21-2009

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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Isn't there a PLL on board the Virtex 5 device which can generate 266MHz from 200MHz input (200 * 4 / 3)?

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor xavier.gonon
Visitor
6,511 Views
Registered: ‎12-01-2010

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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Thanks for your answer Bob,

 

Yes, there is actually PLL's available in the V5. Thought, I have a buffer problem when I generate the 266Mhz with the PLL.

I buffer the 266 Mhz differential clocks generated with the PLL (BUFG) ans since the infrastructure module already involves an input buffer (IBUFGDS_LVPECL_25) an error occurs (same direction buffers in serie).

 

I tried without buffering the sys_clk_n and sys_clk_p generated by the PLL but it doesn't work since IBUFGDS_LVPECL_25 requires as an input a clock coming out of the chip.

 

The issue I'm facing in the ddr2_infrastructure module is how to get the signal 'sys_clk_ibufg' necessary to generate the controller clocks without having any sys_clk_p or sys_clk_n as inputs of the overall design (whether it is 200 or 266 Mhz).

 

Thanks for your help Bob.

 

Xavier

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Teacher eteam00
Teacher
6,480 Views
Registered: ‎07-21-2009

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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Xavier,

 

You need to customise the MIG-generated files to suit your application.  MIG assumes that the 266MHz clock is sourced off-chip, rather than from a PLL.  You need to manually edit your design source code (including the MIG files) to generate the 266MHz clock in the PLL, and to use the PLL output for the memory controller clock.

 

See this thread.

and this thread

and this reference design.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor xavier.gonon
Visitor
6,469 Views
Registered: ‎12-01-2010

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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Thanks,

 

Actually I managed to have the controller work properly on the ml507 using only the sys_clk diff pair and slightly modifying the infrastructure module.

Now I am facing other issues with the cnstraint file and dqs_ibuf signals but this is another topic ;)

 

Cheers

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Participant jai_pandey
Participant
6,383 Views
Registered: ‎12-17-2009

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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Dear friends! I am using EDK 12.4 to use MPMC for the 32 bit DDR2 (Micron, MT4HT3264HY-667) in ML-507 board with Virtex-5 device(xc5vfx70t-1136). I have used this controller for with three ports. One for the MCI, second for the VFBC Write and third one is for the VFBC read. I have used integrated MIG tool for the ucf generation . The generated ucf file does not provides correct LOC. I have corrected the generated UCF file as per the schematic of the virtex-5 . When I have again used the integrated MIG tool to verify the modified ucf it shows error. In error message it says that the modified UCF should follow the same bank, which is not correct bank. Please let me know how can i obtain the correct ucf with all the necessary timing parameters settings for the delay. Please provide me the correct ucf. I also wish to know the IDELAYCTRL related settings for the MPMC. Thanks in advance
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Teacher eteam00
Teacher
6,380 Views
Registered: ‎07-21-2009

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

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Jai,

 

Please start a new thread.

Please include the MIG error messages, and attach your .UCF file

 

Regards,

 

Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant jai_pandey
Participant
6,350 Views
Registered: ‎12-17-2009

Re: I use ML507. Which port can I LOC the "sys_clk_p"、"sys_clk_n"、"clk_200_p"、"clk_200_n"、"phy_init_done" and "sys_rst_n" in FPGA ?

Jump to solution
Dear Sir, As per your instruction I have posted a new thread related to MIG Version 3.5, in MIG forum. By the system administrator, It has been moved to: http://forums.xilinx.com/t5/EDK-and-Platform-Studio/MIG-V-3-5-does-not-support-correct-LOC-for-MPMC-6-02a-for-ML507/td-p/129502 Please find the detail description of the MIG related problem there and resolve my quarry. thanks
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