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ISERDESE3 CLKDIV setup for DDR2 where CLK is a data strobe (DQS)

Posts: 11
Registered: ‎03-01-2016

ISERDESE3 CLKDIV setup for DDR2 where CLK is a data strobe (DQS)

Looking in UG517 and UG974 IDDRE3 uses a CLKDIV pin. This pin is described as:


"The divided clock input (CLKDIV) is typically a divided version of CLK (depending on the width of the implemented deserialization). It drives the output of the serial-to-parallel converter and the CE module."


In xapp1208 CLKDIV pin is also described further as:


"The number of bits captured is set by the DATA_WIDTH attribute when instantiating an ISERDES component in the design source code. Bits are captured in the ISERDES on the CLK clock, and the ISERDES parallel output is available in the general interconnect using the CLKDIV clock.

CLKDIV is thus a divided version of CLK. When DATA_WIDTH is set to eight and the ISERDES is used in Single Data Rate (SDR) mode, CLKDIV is CLK divided by eight. When the ISERDES is used in Dual Data Rate (DDR) mode, CLKDIV is CLK divided by four. Assuming DATA_WIDTH is set to eight"


Using DDR2 the clock driving CLK is DQS which is a strobe and not a clock. I believe this leaves us with using a general clock buffer with a divide function. (BUFGCE_DIV) as DQS is not a continuous clock. 


Assuming a data width of 8, the BUFGCE_DIV would have a divisor of 4 for the strobe and the output of the BUFGCE_DIV would feed CLKDIV.



1. Is using the BUFGCE_DIV the correct option for dividing the DQS strobe to use as a clock?

2. Are there any other considerations that need to be made for using ISERDESE3 with CLKDIV and the DQS strobe to supply the CLK and CLKDIV?