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Observer chandu_sri
Observer
238 Views
Registered: ‎11-23-2015

Init_calib_complete pin not going high for MIG (DDR2 SDRAM Config) in Vivado 18.3

Hi there,

I am trying to configure MIG in Vivado 18.3 for DDR2 SDRAM. Part number i am using is MT47H64M16HR-25E.

MIG configuration details are as mentioned below:


Vivado Project Options:
Target Device : xc7k410t-ffg900
Speed Grade : -2
HDL : verilog
Synthesis Tool : VIVADO

If any of the above options are incorrect, please click on "Cancel", change the CORE Generator Project Options, and restart MIG.

MIG Output Options:
Module Name : design_1_mig_7series_0_0
No of Controllers : 1
Selected Compatible Device(s) : --

FPGA Options:
System Clock Type : Single-Ended
Reference Clock Type : Use System Clock
Debug Port : OFF
Internal Vref : disabled
IO Power Reduction : ON
XADC instantiation in MIG : Enabled

Extended FPGA Options:
DCI for DQ,DQS/DQS#,DM : enabled
Internal Termination (HR Banks) : 50 Ohms



/*******************************************************/
/* Controller 0 */
/*******************************************************/
Controller Options :
Memory : DDR2_SDRAM
Interface : AXI
Design Clock Frequency : 2500 ps (400.00 MHz)
Phy to Controller Clock Ratio : 4:1
Input Clock Period : 4999 ps
CLKFBOUT_MULT (PLL) : 4
DIVCLK_DIVIDE (PLL) : 1
VCC_AUX IO : 1.8V
Memory Type : Components
Memory Part : MT47H64M16HR-25E
Equivalent Part(s) : --
Data Width : 16
ECC : Disabled
Data Mask : enabled
ORDERING : Normal

AXI Parameters :
Data Width : 32
Arbitration Scheme : RD_PRI_REG
Narrow Burst Support : 0
ID Width : 4

Memory Options:
Burst Length (MR0[1:0]) : 8
CAS Latency (MR0[6:4]) : 5
Output Drive Strength (MR1[5,1]) : Fullstrength
Controller CS option : Enable
Rtt_NOM - ODT (MR1[9,6,2]) : 75ohms
Memory Address Mapping : BANK_ROW_COLUMN

Bank Selections:
Bank: 33
Byte Group T0: DQ[8-15]
Bank: 34
Byte Group T0: Address/Ctrl-1
Byte Group T1: Address/Ctrl-0
Byte Group T2: Address/Ctrl-2
Byte Group T3: DQ[0-7]

System_Clock:
SignalName: sys_clk_i
PadLocation: AH6 Bank: 34

System_Control:
SignalName: sys_rst
PadLocation: No connect Bank: Select Bank
SignalName: init_calib_complete
PadLocation: No connect Bank: Select Bank
SignalName: tg_compare_error
PadLocation: No connect Bank: Select Bank

Kindly help me in solving this issue.

Best Regards,

Chandu sri.V

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6 Replies
Xilinx Employee
Xilinx Employee
208 Views
Registered: ‎08-21-2007

回复: Init_calib_complete pin not going high for MIG (DDR2 SDRAM Config) in Vivado 18.3

Is it a new designed board? Did you try to run example design on it? Please starts with the "general checks" and refer to debugging suggestions according to ug586.

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Observer chandu_sri
Observer
193 Views
Registered: ‎11-23-2015

回复: Init_calib_complete pin not going high for MIG (DDR2 SDRAM Config) in Vivado 18.3

Hi kren,

I forgot to mention in my post that DDR2 on my board is working  with  ISE14.7. as my end requirement is in vivado i had to upgrade and somehow mig is not getting properly configured(init_calib_complete pin not going high).

In vivado i couldn't find any example design in which MIG is configured to DDR2. 

Can you kindly elaborate what "general checks" mean?

I am attaching block design of my project for further reference.

Regards,

Chandu sri.

Block_design_MB_MIG.PNG
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Xilinx Employee
Xilinx Employee
174 Views
Registered: ‎08-21-2007

回复: Init_calib_complete pin not going high for MIG (DDR2 SDRAM Config) in Vivado 18.3

You can create MIG IP from the IP catalog and open IP example design by right clicking the generated xci file. Have you checked IP settings and pinout identical with ISE project?

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Observer chandu_sri
Observer
161 Views
Registered: ‎11-23-2015

回复: Init_calib_complete pin not going high for MIG (DDR2 SDRAM Config) in Vivado 18.3

** I have tried creating MIG IP from the IP catalog and opening IP example design the problem i faced is that the sys_clk is required and the clock needs to be taken from the same bank in which DDR signals are connected(i.e., BANK 34) and i don't have any provision of externally generated differential clock on-board in  bank 34.

I tried connecting diff. clk from other bank wherein implementation failed even after adding below constraint in xdc file .

set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets u_mig_7series_0/u_mig_7series_0_mig/u_ddr2_clk_ibuf/sys_clk_ibufg]

 

** Pinouts are same as ISE project and IP settings are also similar.

In ISE mem_ref_clk is 400MHz( In vivado i am taking it as sys_clk), 

ref_clk is 200MHz( In vivado i am taking it as ref_clk)

In ISE i couldn't find sys_rst pin as external port. in vivado i am taking it as active low and connecting to my external active low reset.

 

 

 

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Xilinx Employee
Xilinx Employee
124 Views
Registered: ‎03-04-2018

回复: Init_calib_complete pin not going high for MIG (DDR2 SDRAM Config) in Vivado 18.3

Hello @chandu_sri 

 

I’m not fully understand your current issue, but I would like to share the information about sys_clk in MIG.

 

UG586 says as an attached file.

https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf

The clock input (sys_clk) can be input on any CCIO in the column where the memory interface is located; this includes CCIO in banks that do not contain the memory interface, but must be in the same column as the memory interface.

 

From your package in UG475(page.48), BANK 32, 33 and 34 is the same column, so it is possible to assign the sys_clk to BANK34.  On the other hand, other BANKs like Bank 12 to 18 is not recommended.

https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf

 

Sys_rst is the asynchronous system reset input and default polarity is active-low.  I think that your sys_rst seems to be fine.

 

Best regards,

kshimizu 

Product Application Engineer Xilinx Technical Support

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

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sys_clk.PNG
pack.PNG
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Xilinx Employee
Xilinx Employee
116 Views
Registered: ‎08-21-2007

回复: Init_calib_complete pin not going high for MIG (DDR2 SDRAM Config) in Vivado 18.3

As mentioned in ug586, the sys_clk can be input on any CCIO in the column where the memory interface is located. Do syou have such a clock? The frequency the sys_clk of  is not necessary to be 200MHz. 

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