04-21-2018 01:49 PM
i am working on kintex ultrascale FPGA based ddrc. Working on User App interface to determine if our Bw requirements are met. I am running at 1600ddr @16 bits wide part. Expect 40gbps. User interface is at 200mhz @128bit wide.
Just wondering what would be my best DDR4 bw utilisation goal in percentages.
What techniques or strategies are needed to get RD/WR Bandwidth around 90%?
any hints or numbers would help me plan.
thanks in advance,
04-23-2018 09:15 AM
First I would take a look at the latest version of PG150 and check out the performance test bench in Chapter 7 (page 248).
The performance test bench allows you to generate an access pattern and it will simulate it and tell you your overall bus efficiency.
Also look at the the Production Specification section starting on page 18 and it gives you some estimated efficiencies based on your access pattern.
Your interface is too narrow so you will never be able to achieve the 40Gbps target you stated.
With a 1.6Gbps interface rate with 16-bit width the theoretical max is 25.6Gbps with no DDR4 overhead, but in real life applications your efficiency will be lower. The speed rating for DDR4 is the maximum data-bit toggling rate so a DDR4-1600 interface has a bitrate of 1.6Gbps and the interface clock is 1/2 the bit rate, so 800MHz.
The most efficient access pattern for our controller is going to be a sequential pattern that rotates through the banks, while making sure to not hit the same GroupFSM back to back, that goes through all the column addresses before picking a new row. The Performance section starting on page 190 shows you the GroupFSM mapping to your address mapping option and device width to make sure you’re switching GroupFSMs with every command. If you don't switch GroupFSMs with every access then you'll have low efficiency. The Performance section talks about this.
If you generate the example design then the out of the box the performance test bench should have a very efficient pattern like this.
04-30-2018 05:32 PM
Thanks for your reply.
I forgot to add in my previous message, I am looking at 2 DDR components i.e. theoretical BW at 25.6*2 = 51.2Gbps.
My question was if its possible to achieve 40Gbps consistently. If so what design strategy I need to adapt and or any guide lines.
You have already touched on my question, that Group FSM's need to be switched to getter better out of interface.
Is there any recommendation on how do you ensure GroupFSM switching at a certain Burst boundry, (Change after x DW of data transfer)?
05-01-2018 08:31 AM
The answers to all your questions can be found in the documentation references I mentioned in my previous post.