UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply

Kintex Ultrascale : MIG DDR3 Calibration too many stages Skipped

Highlighted
Observer
Posts: 41
Registered: ‎12-22-2014

Kintex Ultrascale : MIG DDR3 Calibration too many stages Skipped

Hello,

 

Having not found any topics or information related to that, I do call the community for information.

 

Indeed, as you can see in the image attached to that post, I've got several MIGs in my design, some are passing the calibration some not (due to hardware problems).

 

I'm using Vivado 2016..2 with a Kintex Ultrascale xcku085-flva1517 -1i, My DDR are  MT41K128M16JT-125 (data Width 16, voltage 1.35V, interface speed 1250ps, reference input clock 200MHz, AXI interface is enable)

 

My question is more related to the MIGs that are passsing OK the calibration.

Indeed, in PG150 Version 1.2  of June 8, 2016, Figure 31-4 pages 475, there is a description of the calibration sequence. According to this description, The MIG Calibration should run Write/Read Sanity check 3 and 5 , Wirte DQS to DQ ... ...

 

Looking at the stages on the picture, the calibration of my MIG Skipped those stages.

 

There fore my questions are:

  - is that normal that those stages are skipped, despite the information in PG150?

  - how can I force the calibration to go through those tests ?  it seems that the advices of AR#67253 didn't worked for my case.

 

Thank in advance for your replies.

 

regards

 

Olwefin

Capture_calibration.JPG