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Visitor hungd
Visitor
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Registered: ‎11-20-2017

LPDDR3 MIG PHY Only: Periodic Read insertion

Hi everybody,

I am testing on-board LPDDR3 chip, using my Memory Controller and customized Xilinx LPDDR3 SDRAM IP (MIG). My design was posted here: https://forums.xilinx.com/t5/Memory-Interfaces/Kintex-Ultrascale-LPDDR3-How-to-insert-Periodic-Reads-to-the-PHY/td-p/921247

My test sequence is 100000 User Writes and 100000 User Reads, interleavely. Each of User Commands separated by about 12us, so there are approximately 12 Periodic Reads inserted between two User Commands. Below is capture of post-implemented functional simulation:

lpddr3_post_impl_sim2.png

Now I can write to and read from the LPDDR3 chip. Writes are OK but only about the first 1000 BL8s are read correctly. After that the PHY did not seem to send any data to my MC (I've added some debug signals to check that). I also changed periodic read interval to 0.5us/0.8us/1us/1.2us/1.5us but the problem still remains.

I think the problem is due to my Periodic Read insertion. The MIG PHY works well with Xilinx MC, so maybe my MC lacks something that causes the problem.

1. Does anybody have experience with Xilinx MIG PHY customization, especialy about Periodic Reads?

**********

Also, I've read VT Tracking section starting on page 183, PG150. It is contex of DDR3/4. There is a signal called gt_data_ready which customized MC must control to meet PHY requirement, as below:

ddr34_vt-tracking.pngddr34_vt-tracking2.png

2. Does LPDDR3 Memory Controller need to assert this signal? (There is no gt_data_ready signal in the whole LPDDR3 MIG source code)

3. Does my design with Read/Write commands as above meet this VT tracking specification?

 

Thanks

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