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LPDDR3 ultrascale pin/bank rules

Posts: 12
Registered: ‎04-02-2015

LPDDR3 ultrascale pin/bank rules

according to UltraScale Architecture-Based FPGAs Memory IP v1.4    page 285

a. Address/control:ck_t/ck_c,ca[9:0], and cs_n must be placed in the same byte

but the example design followed doesn't follow this rule in page 288-289,  ca[9:0] are placed in byte group T3,  ck_t/ck_c are placed in  byte group T2, cs_n is placed in byte group T1



Xilinx Employee
Posts: 7
Registered: ‎06-02-2017

Re: LPDDR3 ultrascale pin/bank rules

Hi, Jackfan

PG150 is incorrect. You could check with an example design and they're generated in the same byte and if you try to move one of those signals out of the byte then you'll get an error during implementation that these signals must be in the same byte. 

The error will be fixed in the future.