UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply

LPDDR3 ultrascale pin/bank rules

Highlighted
Visitor
Posts: 12
Registered: ‎04-02-2015

LPDDR3 ultrascale pin/bank rules

according to UltraScale Architecture-Based FPGAs Memory IP v1.4    page 285

3.
a. Address/control:ck_t/ck_c,ca[9:0], and cs_n must be placed in the same byte

but the example design followed doesn't follow this rule in page 288-289,  ca[9:0] are placed in byte group T3,  ck_t/ck_c are placed in  byte group T2, cs_n is placed in byte group T1