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Visitor bonsaipappel
Visitor
3,030 Views
Registered: ‎03-24-2010

MIG 3.7 - ModelSim Simulation

Hi,

 

I'm having a strange behavior while simulating my Design including a DDR3 Memory interface (MIG 3.7).

I'm using the follofwing confiduration of the ddr3_model:

vlog  +incdir+. +define+x2Gb +define+sg15E +define+x8 "../../vlog/tb/ddr3_model.v"

 

My design has a 32 bit communication bus from where I can talk to the design. So I'm able to write 32 Bit parallel.

I have some internal Logic which allows me to initiate a 32 bit wide ddr3 read or write access.

 

What I try to do:

I have to write 2 data packets (each 320 bytes wide) to the DDR3 memory.

I'm writing the entire 2 frames (together 640 bytes) one by one into the DDR3 Memory.

The first data packet reaches from Address 0 to 316 and the second data packet from 320 to 636.

After writing the data into the DDR3 memory i want to read it back. If I read the data one by one without pause I get back all data correctly. But if I insert a pause of 1us between the read of the last 32 bit from packet one (ddr address 316) and the begining of the read of packet two (ddr address 320) all data from packet two are invalid.

 

To Make this more clear:

 

The working algorithm:

1: DDR3-Write all 640 byte (packet one and two) from address 0 to address 636 (4 byte per transfer)

2: DDR3-Read all 640 byte (packet one and two) from address 0 to address 636 (4 byte per transfer) --> data is valid

 

The NOT-Working algorithm:

1: DDR3-Write all 640 byte from address 0 to address 636 (4 byte per transfer)

2: DDR3-Read all 320 byte from address 0 to address 316 (4 byte per transfer) (first packet) --> Data is valid

3: Wait 1 us - do nothing

4: DDR3-Read all 320 byte from address 320 to address 636 (4 byte per transfer) (second packet) --> Data is invalid

 

I know this hard to describe but I hope someone can understand the problem.

 

What I already tried:

1: Increase the MEM_BITS value in the ddr3_model_parameters.vh --> no change

2: set the MAX_MEM define in the ddr3_model.v --> Simulator exits with an error that "argument 1 of $fseek is invalid". In the log I can see that there are "X" during the DDR3 initialisation 

3: Set the read start address from the second data packet to 0: --> following algorithm:

1: DDR3-Write all 640 byte from address 0 to address 636 (4 byte per transfer)

2: DDR3-Read all 320 byte from address 0 to address 316 (4 byte per transfer) (first packet) --> Data is valid

3: Wait 1 us - do nothing

4: DDR3-Read all 320 byte from address 0 to address 316 (4 byte per transfer) again

--> Now I'm getting the data from packet two even though the start address is the same as the one of data packet one

 

 

Is there any known bug in the Micron Simulation Model which is causing this behavior?

Could this be a limitation of the simulation model?

 

I am grateful for any suggestions.

 

Best regards,

Volker

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Xilinx Employee
Xilinx Employee
3,023 Views
Registered: ‎08-16-2007

Re: MIG 3.7 - ModelSim Simulation

I doubt there is a problem with the memory model but I could be wrong. Can you provide a waveform or screen shot illustrating how you are driving the User Interface for the invalid case?

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