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Observer manninosi
Observer
1,421 Views
Registered: ‎06-01-2017

MIG 7 Series clock differences

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Hello, 

 

I'm currently using the Opal kelly XEM7350 board that utilizes the Kintex-7 FPGA. I employed the recommended parameters form opal kelly from this link on page 18. The specified design clock frequency is 800 MHz with a PHY to Controller ratio of 4:1. The input system clock is the 200 MHz LVDS oscillator that is located on the Opal Kelly board. 

 

I noticed the write and read state machines were not working as expected, so I turned on the debug ports to try and located the issue. The ila_basic[15] signal is high which indicates there is an error in the MPR stage of calibration. 

 

I sent out clocks from the UI-clk and mem_clk to pins that I am reading to on an oscilloscope. The current UI_clk is read to be 100 MHz and the mem_clk is read to be 400 Mhz. This is half the value from the specified design frequency when generating the IP core. Is this an issue that has been seen before with they clock discrepancies? 

 

Let me know if I need to provide any additional or specific information to clarify the problem. 

 

Thank you, 

 

-Mitch

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1 Solution

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Observer manninosi
Observer
1,798 Views
Registered: ‎06-01-2017

Re: MIG 7 Series clock differences

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Hi @ryana

 

Sorry for the late reply!

 

I spent some time reviewing my state machine that resets the MIG 7 IP Core and discovered I was not appropriately entering the "reset state". Once I cleared that issue the calibration signal went high, so now I only need to create "write" and "read" state machines. 

 

Thank you for your time! 

 

-Mitch

8 Replies
Voyager
Voyager
1,368 Views
Registered: ‎06-20-2017

Re: MIG 7 Series clock differences

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Did you contact Opal Kelly?

Adaptable Processing coming to an IP address near you.
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Observer manninosi
Observer
1,360 Views
Registered: ‎06-01-2017

Re: MIG 7 Series clock differences

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I haven't emailed opal kelly since it seems that the clocking difference is occuring within the MIG IP core. I have probed the 200 MHz oscillator from the Opal Kelly board. It seems that the system is going through the calibration steps, but fails once it reaches the MPR stage of calibration. 

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Moderator
Moderator
1,331 Views
Registered: ‎11-28-2016

Re: MIG 7 Series clock differences

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Hello @manninosi,

 

I looked at the XEM7350 reference manual you linked and on page 18 it gives two different configurations depending on the specific SKU you purchased.  For the XEM7350-K70T it says it will generate a 400MHz DDR3 interfaces, so a 100MHz ui-clk, and this aligns with the behavior you're describing.  For the XEM7350-K160T it says it will generate a 800MHz DDR3 interface.  My next steps would be to double check the specific board your purchased.

Observer manninosi
Observer
1,320 Views
Registered: ‎06-01-2017

Re: MIG 7 Series clock differences

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Hi @ryana!

 

Sorry I was not specific in my initial reply. I am using the XEM-K160T which specifies the 800 MHz signal. 

 

Also, as an additional check I generated a core with the XEM-K70T parameters (400 MHz) signals and probed the clocks. Once again the clocking signals were reduced by half of the specified parameters in the IP core. 

 

Thanks, 

 

-Mitch

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Moderator
Moderator
1,313 Views
Registered: ‎11-28-2016

Re: MIG 7 Series clock differences

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Hello @manninosi,

 

Have you verified that the 200MHz clock on the board is running at 200MHz?  This looks like the sys_clkp/n pin at AC4/AC3.  When you configure the MIG do you set the system clock to the 200MHz clock source, set the reference clock to use System Clock, and during the last page of the pin assignment are you setting the System Clock PIn Selection to  Bank 34 pins AC4/AC3?

 

Observer manninosi
Observer
1,282 Views
Registered: ‎06-01-2017

Re: MIG 7 Series clock differences

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Hi @ryana

 

I checked through my design and ensured that Bank34 has the system clock pin selection to Bank 34 pins AC4/AC3. I send the LVDS clocking signal to a IBUFG and connected it to a pin that I read with an oscilloscope and found it to be 200 MHz. 

 

I sent the other clocking signals, the UI_clk and Mem_clk from the MIG core to pins to check those as well and they read half of what they are indicated to be when setting up the IP core. 


Checking the debug signals I'm still showing ILA_Basic[15] to be high indicating an error during the MPR stage of calibration. 

 

Thank you for taking your time and helping me out with this issue! 

 

-Mitch

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Moderator
Moderator
1,272 Views
Registered: ‎11-28-2016

Re: MIG 7 Series clock differences

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Hello @manninosi,

 

Can you attach your XCI, mig*.prj, and XDC/UCF files for the design so I can take a look?

Observer manninosi
Observer
1,799 Views
Registered: ‎06-01-2017

Re: MIG 7 Series clock differences

Jump to solution

Hi @ryana

 

Sorry for the late reply!

 

I spent some time reviewing my state machine that resets the MIG 7 IP Core and discovered I was not appropriately entering the "reset state". Once I cleared that issue the calibration signal went high, so now I only need to create "write" and "read" state machines. 

 

Thank you for your time! 

 

-Mitch