01-28-2017 11:29 PM
I am using the 7 series MIG and have to use an AXI interface because of all the custom read/write logic and modules I have in my system. It really helps because I can use an AXI arbiter with many slave ports which let me easily add modules here. But I am running across a bandwidth issue with the AXI.
I've found that the MIG AXI interface is only single-acceptance, which really hurts any transfers that are not maximum-length bursts. Even if I set my arbiter to have buffers and high acceptance, the latency on the MIG seems to be 2 clock cycles minimum between commands which won't work for this system.
Does anybody know how I can get the MIG to accept data without any gaps? Switching to the native interface isn't an option for me because of all of the AXI IP in the system, so any help would be greatly appreciated!
01-29-2017 04:18 PM
Looks like I'm having the exact same issue described here https://forums.xilinx.com/t5/Memory-Interfaces/MIG
According to the moderator, a bugfix was supposed to be released (I am using v2.4 rev 1), but it is still acting the same way. There was also mention of some patch, but I'm not sure what was being referred to.