UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer zofre_rauhut
Observer
7,867 Views
Registered: ‎03-20-2013

MIG-DDR2-Control Place-Error: [Place 30-53] IDELAYCTRL instances ... have same IODELAY_GROUP 'IODELAY_MIG' but their RST signals are different.

Jump to solution

Hi,

I have a design using two DDR2-RAM-Controllers, each controller with its own SYS_CLK, CLK_REF and RST.

 

During place I got the following 2 errors (the path-names are replaced by ..... to keep the error message as short as possible):

  

[Place 30-53] IDELAYCTRL instances ...  and ... have same IODELAY_GROUP 'IODELAY_MIG' but their RST signals are different.

 

[Place 30-53] IDELAYCTRL instances ...  and ... have same IODELAY_GROUP 'IODELAY_MIG' but their REFCLK signals are different.

 

 

What would be the solution for this problem?

Best Regards

Bodo

 

0 Kudos
1 Solution

Accepted Solutions
Observer zofre_rauhut
Observer
10,943 Views
Registered: ‎03-20-2013

Re: MIG-DDR2-Control Place-Error: [Place 30-53] IDELAYCTRL instances ... have same IODELAY_GROUP 'IODELAY_MIG' but their RST signals are different.

Jump to solution

Hi,

I got it working with the following modifications:

-> in the top-entity I changed the generic-parameter "IODELAY_GRP" for each MIG-DDR2-Module

-> the default value for the  "IODELAY_GRP" is "IODELAY_MIG"

-> after the modifcation the generic parameter for the 1st "IODELAY_GRP" was changed to "IODELAY_MIG_01"

-> and the generic parameter for the 2nd "IODELAY_GRP" was changed to "IODELAY_MIG_02"

-> after this modification the two DDR2-Controller are working

 

Best regards

Bodo

 

0 Kudos
7 Replies
Xilinx Employee
Xilinx Employee
7,861 Views
Registered: ‎08-16-2007

Re: MIG-DDR2-Control Place-Error: [Place 30-53] IDELAYCTRL instances ... have same IODELAY_GROUP 'IODELAY_MIG' but their RST signals are different.

Jump to solution

You need to locate the IODELAY_GROUP in the RTL for each controller and assign a unique name for each or you can regenerate a multi-controller design using MIG and MIG will automatically handle this for you.

0 Kudos
Observer zofre_rauhut
Observer
7,858 Views
Registered: ‎03-20-2013

Re: MIG-DDR2-Control Place-Error: [Place 30-53] IDELAYCTRL instances ... have same IODELAY_GROUP 'IODELAY_MIG' but their RST signals are different.

Jump to solution

Hi,

>You need to locate the IODELAY_GROUP in the RTL for each controller

the IODELAY_GROUP is located in the RTL for each controller, it is generated automatically by the MIG.

because I used two seperate DDR2-RAM-Controller the IODELAY_GROUP is located under the controller.

attached the structure of the 2 DDR2-RAM-controller: the iodelay_ctrl is located under each controller

 

>and assign a unique name for each

does this mean, I have to rename the instance-name for each IODELAY_GROUP manually?

 

>or you can regenerate a multi-controller design using MIG and MIG will automatically handle this for you

for a DDR2-Design this is not possible, MIG only supports multi-controller design for a DDR3-design

Unbenannt.jpg
Unbenannt.jpg
0 Kudos
Observer zofre_rauhut
Observer
10,944 Views
Registered: ‎03-20-2013

Re: MIG-DDR2-Control Place-Error: [Place 30-53] IDELAYCTRL instances ... have same IODELAY_GROUP 'IODELAY_MIG' but their RST signals are different.

Jump to solution

Hi,

I got it working with the following modifications:

-> in the top-entity I changed the generic-parameter "IODELAY_GRP" for each MIG-DDR2-Module

-> the default value for the  "IODELAY_GRP" is "IODELAY_MIG"

-> after the modifcation the generic parameter for the 1st "IODELAY_GRP" was changed to "IODELAY_MIG_01"

-> and the generic parameter for the 2nd "IODELAY_GRP" was changed to "IODELAY_MIG_02"

-> after this modification the two DDR2-Controller are working

 

Best regards

Bodo

 

0 Kudos
Visitor xilinxnii
Visitor
7,541 Views
Registered: ‎12-09-2013

Re: MIG-DDR2-Control Place-Error: [Place 30-53] IDELAYCTRL instances ... have same IODELAY_GROUP 'IODELAY_MIG' but their RST signals are different.

Jump to solution

I have the same problem with two chip2chip modules,
but I couldn't resolve it by this way, becouse chip2chip has no sources
and I could not change his parameters...
How it do?

0 Kudos
7,514 Views
Registered: ‎10-25-2009

Re: MIG-DDR2-Control Place-Error: [Place 30-53] IDELAYCTRL instances ... have same IODELAY_GROUP 'IODELAY_MIG' but their RST signals are different.

Jump to solution
Hi,
I used same method, but vivado report error info:
[Place 30-51] IDELAYCTRL elements have been found to be associated with IODELAY_GROUP 'IODELAY_QDR', but the design does not contain IODELAY elements associated with this IODELAY_GROUP.

do you know what is its meaning, thank you

0 Kudos
Visitor xilinxnii
Visitor
7,507 Views
Registered: ‎12-09-2013

Re: MIG-DDR2-Control Place-Error: [Place 30-53] IDELAYCTRL instances ... have same IODELAY_GROUP 'IODELAY_MIG' but their RST signals are different.

Jump to solution

I think this is due to the internal structure of C2C , which is hidden by the manufacturer (RSA+AES).
in Verylog, to set the IODELAY group in the *. v source element is written string 

(* IODELAY_GROUP = "C2C_PHY_group" *)

in XDC we can only use existing groups, created in v (forexample: C2C_PHY_group)


Thus, when a module type Master should have to write *. v (* IODELAY_GROUP = "C2C_PHY_group_M" *), and in creating Slave (* IODELAY_GROUP = "C2C_PHY_group_S" *),

 

Thus in XDC we would just write :
set_property IODELAY_GROUP C2C_PHY_group_M [get_cells ...]
set_property IODELAY_GROUP C2C_PHY_group_S [get_cells ...]

Vivado in C2C always writes (* IODELAY_GROUP = "C2C_PHY_group" *)

 

By My mind that can solve this problem only by the manufacturer , as sources C2C closed.


0 Kudos
Visitor jangobin
Visitor
5,476 Views
Registered: ‎07-22-2014

Re: MIG-DDR2-Control Place-Error: [Place 30-53] IDELAYCTRL instances ... have same IODELAY_GROUP 'IODELAY_MIG' but their RST signals are different.

Jump to solution

Hi,

 

I am having a similar problem. I instantiate 4 chip2chip modulles in a virtex2000 device.

(2 masters and 2 slaves)

 

As decibed by xilinxii I tried to aply the following contraints :

 

set_property IODELAY_GROUP PCIe_C2C_PHY_group_M [get_cells {U_PCIe_C2C_bridge/PCIe_C2C_i/axi_chip2chip_0/inst}]
set_property IODELAY_GROUP PCIe_C2C_PHY_group_S [get_cells {U_PCIe_C2C_bridge/PCIe_C2C_i/axi_chip2chip_1/inst}]
set_property IODELAY_GROUP C2C_PHY_group_M [get_cells {U_C2C_wrapper/C2C_i/axi_chip2chip_0/inst}]
set_property IODELAY_GROUP C2C_PHY_group_S [get_cells {U_C2C_wrapper/C2C_i/axi_chip2chip_1/inst}]

 

Altough Vivado accept these contraints, I still have the issue...

 

How can I make Vivado understand that I would like to use a different IODELAY_GROUP for each chip2chip instance?

Are the above contraints correct?

 

In Advance thanks for your help!

 

Jan Gobin

0 Kudos