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MIG DDR4 Example design



I need to inderstand the simulation of the MIG DDR4 example design:

- After the calibration is completed, how refresh the DDR and with which instruction ?

- The MIG receive/send data from/to S_AXI interface to/from DQ interface of the DDR. Why I don't find the same data in the two interfaces at the same clock cycle or after some cycles ?





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Registered: ‎11-28-2016

Re: MIG DDR4 Example design

Hello @Anonymous,


By default the refreshes are automatically scheduled by the controller and the user doesn't have to do anything.


There is the option to enable user refresh commands when configuring the IP which allows you to send the refresh request through the app_interface. The Maintenance Command section in PG150 talks about this feature.  This option isn't available when using the AXI interface option.



For the second question I'm not exactly sure what you're asking but the reason you don't see the same data in two places after a clock cycle is that it takes multiple clock cycles for the command to go through the AXI shim, then get scheduled in the controller, then have the controller issue the required commands (precharge/activate/write/read) before the data appears on the interface.  I recommend running the example design simulation so you can see the amount of time it takes from when the command is accepted on the AXI interface to when the command is executed on the DRAM interface.