03-13-2018 02:18 AM
I use in my design a MIG-DDR4 IP core with memory reference MT40A512M16HA.
In the implementation phase, I had this error:
[Mig 66-99] Memory Core Error - [TOP_LEVEL_i/ddr4_MIG] Port(s) ddr4_ck_c,ddr4_ck_t,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_adr,ddr4_ba,ddr4_ba,ddr4_bg,sys_clk_n,sys_clk_p,ddr4_bg,ddr4_cs_n,ddr4_cke,ddr4_odt,ddr4_act_n,ddr4_reset_n,ddr4_dqs_c,ddr4_dqs_t,ddr4_dm_n,ddr4_dq,ddr4_dq,ddr4_dq,ddr4_dq,ddr4_dq,ddr4_dq,ddr4_dq,ddr4_dq is/are not placed. Assign all ports to valid sites.
03-13-2018 07:37 AM
The error message is just stating that you have not placed these following DDR4 Memory IP I/O's. I highly recommend looking into UG899 Chapter4: I/O Planning for UltraScale Architecture Memory IP found here:
We have a tool called the Byte Planner that you can use to assign Memory I/O's. It takes care of all the placement rules we have in Product Guide 150 for you.
If you have any other issues, please let us know.
03-14-2018 04:04 AM
I placed the I/Os of my memory IP and now I have this error:
[Common 17-49] Internal Data Exception: Site type arc id '15' out of range. The pips vector has 11 elements. The site type name is 'BITSLICE_RX_TX'.
03-14-2018 08:00 AM
Which version of Vivado are you using? Are you using default Synth/Implementation Strategies? Do you run into this issue using our example design?
03-14-2018 08:26 AM - edited 03-14-2018 09:10 AM
I use Vivado v2017.3.1 with default Synth/Implementation Strategies.
No problem with your example design.
04-06-2018 11:23 AM
When you tested with the example design, did you use the same pin locations in the top level XDC as what you are looking to do in your application?
Can you tell me how you changed the pins to get past the first error? I'd like to know what tool or tcl commands you used and in which stage of the build you did this.
Sometimes this happens if the system clock driving the IP is not placed in a valid location, you'd see another warning related to if that was the case.
Sometimes this happens if the pin constraints are changed after synthesis. There is some physical configuration of the memory IP that happens during synthesis that links pins to the hard block. Occasionally this can get out of sync.
We can check this by opening the synthesized design and running the tcl command implement_mig_cores -verbose
Send the output over and we can take a look to see if anything stands out.
There is a chance that regenerating the output products and starting the build over again will work too.