01-10-2017 08:54 AM
I currently have a design developed on Xilinx VC709, in the design, the incoming data is received from multiple sensors with a known scrambled order (sensor1, s4, s2, . .) in stream format, data is then buffered and written to DDR3 via MIG UI and my state machine, where I can control when to write where to write in DDR3, as well as when and where to read.
Now, I have to move the design to actual system that we purchased, the vendor packages some of the IPs into their own BSIP (Board support IP), and mig controller is one of IPs but it is in AXI intead of UI.
I have been looking at the IP catalog/AXI Infrastructure as well as generate block design in Vivado 2015.4, I dont seem to find anything that would give me the flexibility to control the read/write address. I would like to be able to unscramble the channels as I write or as I read.
I feel that AXI provides quick connections but lacks of flexibility. Any suggestions from the experts would be appreciated greatly.
01-30-2017 04:52 AM
Can you elaborate what is the exact issue you are facing with the AXI addressing.
As the AXI is byte addressing and depending on the configuration you may need to buffer you data to match the AXI requirements and should be able to write and read similar to you Native interface.
Below thread has some details on the aggregate addressing when AXI is used.