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Visitor abs00169
Visitor
8,288 Views
Registered: ‎01-21-2009

MIG customisation within the AC701 TRD - errors out

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I have been developing my code on an AC701 board and have reached the point where I want to re-target to my own implementation of hardware. However on re-customising the MIG I get the following error :-

 

 [IP_Flow 19-3461] Value ' ' is out of the range for parameter 'BOARD_MIG_PARAM(BOARD_MIG_PARAM)' for IP 'mig_7x' . Valid values are - Custom
 [IP_Flow 19-3461] Value ' ' is out of the range for parameter 'BOARD_MIG_PARAM(BOARD_MIG_PARAM)' for IP 'mig_7x' . Valid values are - Custom
 [IP_Flow 19-3439] Failed to restore IP 'mig_7x' customization to its previous valid configuration.

 

What's interesting is that when I go back to the original TRD files and try to do the same I get the exact same error when re-customising the MIG. So the original TRD files also seem to have something wrong.

 

Where should I be setting the parameter that it says cannot be '' (blank)? I've searched through the MIG settings and the project settings but cannot find it.

 

The AC701 TRD I'm using is the 2014.1 version which I believe is the latest. I am also using the 2014.1 Vivado software release.

 

Any help will be appreciated.

 

Best regards,

 

David

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Visitor abs00169
Visitor
13,843 Views
Registered: ‎01-21-2009

Re: MIG customisation within the AC701 TRD - errors out

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This is what appears to be happening :-

 

The MIG ip included within the ac701 TRD seems to require the BOARD_MIG_PARAM(BOARD_MIG_PARAM) to be something other than '' (blank).

 

There is an entry within the Vivado XPR project file (a7_base_trd.xpr)  that corresponds to this :-

    <Option Name="BoardPart" Val=""/>

 

Trying to re-customising the mig errors out because of this.

 

The entry can be set to something non blank if the ac701 board is chosen when creating a new project (instead of choosing the 7a200t part). However this locks out the mig ip from the TRD with the status that it wasn't built with these settings so this seems to be some protection for using mig ip from one design in another design.

 

The solution is to re-create the mig from scratch with all the same settings. I have verified this works in the ac701 board and now allows me to re-customise it for my own design.

 

PS You must re-create the ip, not just copy it as the copy has the same problem.

 

Hope this helps someone else.

 

David

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5 Replies
Xilinx Employee
Xilinx Employee
8,274 Views
Registered: ‎07-11-2011

Re: MIG customisation within the AC701 TRD - errors out

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Hi,

 

If you are using AC701 the pinout will be fixed so if you can run the board automation i think there should not be any issue, did you try it and see the same behaviour?

 

Also Vivado 2014.1 and .2 have some known issues with respect to mig.prj so please perefer to use Vivado 2014.4

http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/MIG-sys-clk-AC701-board-settings/td-p/480742

 

 

Below links can help you with the flow and ready design and also pinout files

https://secure.xilinx.com/webreg/clickthrough.do?cid=377650&license=RefDesLicense&filename=rdf0223-ac701-mig-c-2014-4.zip&languageID=1

 

 

https://secure.xilinx.com/webreg/clickthrough.do?cid=377640&license=RefDesLicense&filename=xtp225-ac701-mig-c-2014-4.pdf&languageID=1

 

You can try to import existing pinout in the read ucf option or go for Verify pin changes and update design option in second page of MIG GUI

 

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Visitor abs00169
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8,270 Views
Registered: ‎01-21-2009

Re: MIG customisation within the AC701 TRD - errors out

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Hello vsrunga,

 

Thanks for your reply which I didn't actually understand. What did you mean by board automation?

 

As I am now targetting a different arrangement of DDR chips on my own board not on the AC701 I cannot generate IP products for this new arrangement as I can't get the mig to save out my settings.

 

I am surprised that I seem to be the only one to have hit this problem unless I have something incorrectly set up somewhere hence the reason I went back to the original TRD files and try to recustomise the mig there.

 

Best regards,

 

David

 

 

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Xilinx Employee
Xilinx Employee
8,259 Views
Registered: ‎07-11-2011

Re: MIG customisation within the AC701 TRD - errors out

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Hi,

 

If you are not targetting AC701 board then please upgrade your tool to 2014.4,  if you see the same erro please copy your project and MIG GUI generation snapshots to any word document and upload them here along with your mig.prj and xc, so that I can try to replicate the behaviour at my end and update you.

Also did you try the same MIG configuration in a new project or in another machine and is the same error seen?

Is this in Linux or Winows and which OS?

If you have mig.prj and xdc try verify pinout and update design option too.

 

 

Regards,

Vanitha

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Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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Visitor abs00169
Visitor
13,844 Views
Registered: ‎01-21-2009

Re: MIG customisation within the AC701 TRD - errors out

Jump to solution

This is what appears to be happening :-

 

The MIG ip included within the ac701 TRD seems to require the BOARD_MIG_PARAM(BOARD_MIG_PARAM) to be something other than '' (blank).

 

There is an entry within the Vivado XPR project file (a7_base_trd.xpr)  that corresponds to this :-

    <Option Name="BoardPart" Val=""/>

 

Trying to re-customising the mig errors out because of this.

 

The entry can be set to something non blank if the ac701 board is chosen when creating a new project (instead of choosing the 7a200t part). However this locks out the mig ip from the TRD with the status that it wasn't built with these settings so this seems to be some protection for using mig ip from one design in another design.

 

The solution is to re-create the mig from scratch with all the same settings. I have verified this works in the ac701 board and now allows me to re-customise it for my own design.

 

PS You must re-create the ip, not just copy it as the copy has the same problem.

 

Hope this helps someone else.

 

David

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Xilinx Employee
Xilinx Employee
8,221 Views
Registered: ‎07-11-2011

Re: MIG customisation within the AC701 TRD - errors out

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Hi,

 

Thannks for your update!

So looks clue of generating a new project helped to narrow down the issue.

It is true that IP will be locked when the settings that it is generated with do not match the current project but in that case instea you will not be allowed to do re customization at all and need to place a new block or start a new project.

 

Regards,

Vanitha

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