UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer tamiro
Observer
596 Views
Registered: ‎09-11-2017

MIG generates xdc with hsul_12 slew rate fast can I override to slow?

Hello,

My platform has Artix7 FPGA and LPDDR2 memory.

The MIG generated XDC sets the IOs for Data and Address to HSUL_12 slew rate FAST.

Signal integrity simulations for a new board (with slight modifications) shows that I need to configure the io's to:

Slew rate : slow.

1. Is there a setting in the MIG that will change its generated xdc accordingly?

2. If I override the XDC manually should I expect misbehaiviour?

 

Thanks.

0 Kudos
2 Replies
Moderator
Moderator
568 Views
Registered: ‎09-18-2014

Re: MIG generates xdc with hsul_12 slew rate fast can I override to slow?

Tamiro,

 

 

1. Is there a setting in the MIG that will change its generated xdc accordingly?

-You should be able to just change the XDC file manually or through the IO port list/tab in IO/pin planner mode but don't expect any support from Xilinx when doing something like this that is not doable through their IPs. There's usually a reason why certain options don't exist within the IP and that is the case with any customized or customer edited/moded IPs. 

 

2. If I override the XDC manually should I expect misbehaiviour?

-XDC is a constraints file. What do constraints usually effect? Check device timing to see if it still passes setup/hold. I am not too familiar with memory interfaces in general but doesn't JEDEC specify derating tables for LPDDR2? I've seen them for DDR2/3 for all frequencies and slew rates. In any case, there will be some work to do and based off of the IP options Xilinx probably hasn't characterized and will not support this since it is not an option in the IP nor is there supportive Xilinx documentation for doing so. 

 

Regards,

T

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Observer tamiro
Observer
519 Views
Registered: ‎09-11-2017

Re: MIG generates xdc with hsul_12 slew rate fast can I override to slow?

I have run a test case on my existing design

where all works fine at slew rate fast

and although it passes device timing without an error

With slow at my original LPDDR2 frequency the DDR interface does not work.

When I lowered the DRAM (and MIG) to it's lowest supported frequency (200MHz DDR)

It also works fine.

I'm not sure what to conclude:

1. Signal integrity simulation is not too accurate? (according to it I was suppose to be just fine at my original freq. with slew rate slow).

2. FPGA Timing checks has little to add here since it's an interface to the board and external IC.

 

   

0 Kudos