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Explorer
Explorer
3,472 Views
Registered: ‎05-31-2017

MIG initialisation fails [Artix 7 and DDR3]

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Hi everyone,

 

I have a MIG 7 series, a DDR3 MT41K64M16-107, and an Artix7 axc7a50t.

In simulation, MIG initialize the DDR, and it's ok.

But in reality, I have some trouble.

 

On my obard, I have a 125MHz differential clock and a 27 MHz.

I use the 27MHz with a Clocking wizard to generate 200MHz for ref_clk and 250MHz for sys_clk

I use the 125Mhz for sys_clk.

 

When i program the device :

- ddr3_ck_n and ddr3_ck_p stay high (at Vref).

- ddr3_rst_n works (toggle when I press reset button).

- init_calib_complete stay low.

- ui_clk_out of MIG is ok

 

Is there something to do?

 

Thanks guys.

 

 

---------------------------------------------------------------

MIG summary : 

 

Vivado Project Options:

Target Device : xc7a50t-fgg484

Speed Grade : -3

HDL : vhdl

Synthesis Tool : VIVADO

 

If any of the above options are incorrect, please click on "Cancel", change the CORE Generator Project Options, and restart MIG.

 

MIG Output Options:

Module Name : mig_7series_0

No of Controllers : 1

Selected Compatible Device(s) : xc7a75t-fgg484, xc7a100t-fgg484

 

FPGA Options:

System Clock Type : Differential

Reference Clock Type : No Buffer

Debug Port : OFF

Internal Vref : disabled

IO Power Reduction : OFF

XADC instantiation in MIG : Enabled

 

Extended FPGA Options:

DCI for DQ,DQS/DQS#,DM : enabled

Internal Termination (HR Banks) : 50 Ohms

 

/*******************************************************/

/* Controller 0 */

/*******************************************************/

Controller Options :

Memory : DDR3_SDRAM

Interface : NATIVE

Design Clock Frequency : 2000 ps ( 0.00 MHz)

Phy to Controller Clock Ratio : 4:1

Input Clock Period : 8000 ps

CLKFBOUT_MULT (PLL) : 8

DIVCLK_DIVIDE (PLL) : 1

VCC_AUX IO : 1.8V

Memory Type : Components

Memory Part : MT41K64M16XX-107

Equivalent Part(s) : MT41K64M16TW-107

Data Width : 16

ECC : Disabled

Data Mask : enabled

ORDERING : Strict

 

AXI Parameters :

Data Width : 128

Arbitration Scheme : RD_PRI_REG

Narrow Burst Support : 0

ID Width : 4

 

Memory Options:

Burst Length (MR0[1:0]) : 8 - Fixed

Read Burst Type (MR0[3]) : Sequential

CAS Latency (MR0[6:4]) : 7

Output Drive Strength (MR1[5,1]) : RZQ/7

Controller CS option : Enable

Rtt_NOM - ODT (MR1[9,6,2]) : RZQ/6

Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off

Memory Address Mapping : BANK_ROW_COLUMN

 

 

Bank Selections:

Bank: 34

Byte Group T0: DQ[8-15]

Bank: 35

Byte Group T0: Address/Ctrl-0

Byte Group T1: Address/Ctrl-1

Byte Group T2: Address/Ctrl-2

Byte Group T3: DQ[0-7]

 

System_Clock:

SignalName: sys_clk_p/n

PadLocation: K4/J4(CC_P/N) Bank: 35

 

System_Control:

SignalName: sys_rst

PadLocation: No connect Bank: Select Bank

SignalName: init_calib_complete

PadLocation: No connect Bank: Select Bank

SignalName: tg_compare_error

PadLocation: No connect Bank: Select Bank

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
3,879 Views
Registered: ‎10-19-2015

Re: MIG don't generate ddr3_clk

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Hello @pgrangeray

Based on what we've discussed I'm am surprised you see init_calib_complete assert. Did you add the delay constraint back in?

 

The trace lengths need to be deskewed and need to include the package delays. 

If the hardware guidelines are not followed we can't fix the IP with code. 

 

The fastest path to resolution is to redesign the board and meet all of our design guidelines. 

The slower path is to send me your board files so I can review and then confirm that you need to follow all our design guidelines. We will follow the debugging guide in UG586. This debugging process will use an example design, and we will exchange ILA captures, PCB files, and your schematic files. I will try to isolate the most likely root cause of the failure and then ultimately recommend that the board gets redesigned following all of our guidelines. 

 

The path forwards with the lowest risk and the quickest product release is to redesign the board to meet all of our stated design guidelines I can look over the PCB and schematic files with you and we can evaluate the chance for future success. 

 

You mentioned earlier that there are no capacitors in the design. I hope that is not true, however if it is please be aware that the FPGA power requirement is 2% ripple voltage from the DC operating point. The typical DDR ripple voltage is 60mV, however our guidelines recommend 2% from the operating point there as well. Capacitors help with that ripple. 

 

The top 3 contributors are likely trace length matching, power ripple, termination. 

 

Also make sure to watch out that you are not changing PCB levels too much. Finally, make sure you have plenty of additional ground vias around the DRAM for better signal integrity. 

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27 Replies
Moderator
Moderator
3,438 Views
Registered: ‎11-28-2016

Re: MIG don't generate ddr3_clk

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Hello @pgrangeray,

 

The first thing I would do is go through the General Checks section of the DDR3/DDR2 debugging chapter in UG586 starting on page 232 to make sure the basics are all OK.  Here's a link to the latest version:

https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf

 

Then I would reconfigure the IP to enable the Debug signals and then see if the MIG is running calibration or gets stuck before it even starts.  Look at the Determining the Failing Calibration Stage section of UG586 starting on page 235.

 

From the sounds of it though something more fundamental is happening and you're not getting to the part where calibration is running.  Generate the design with the debug signals enabled and then mark the MMCM_LOCKED and PLL_LOCKED signals in the DDR Infrastructure as debug and add them to an ILA.  Generate the bitstreams and see if these signals are asserted.  If there not asserted then you have a clocking or clock quality problem.  Also check the top level reset in to the MIG core to see if it's the correct polarity for the MIG configuration.  Check this the same way as checking the LOCKED signals buy marking it as debug and adding it to an ILA core. 

 

The General Checks section goes over this but I would also double check the clock sources on the board, make sure the XDC constraints for the pin-out and I/O standards for the clock sources are correct, and they're following the MIG clocking guidelines.  The MIG clocking guidelines start on page 210 of UG586. Double check all the voltage rails and double check that the MIG IP configuration matches everything in and on the hardware.

Explorer
Explorer
3,426 Views
Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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Hi @ryana

 

Thank you.

I will try to run the example design with debug on my board.

 

See you later...

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Explorer
Explorer
3,419 Views
Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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@ryana

 

So, now the example design is running on my board with debug.

 

phaselocked is ok

 

dqsfound is ok

 

There is a Write level error.

PHY init sate stay at INIT_WRLVL_WAIT (value 7).

Write Level state oscillates betweend 7 (WL_FINE_INC) , 8 (WL_WAIT) and 9 (WL_EDGE_CHECK).

And wl_edge_detect_valid toggles.

 

See screenshot attached.

 

 

No other error.

 

Any idea?

 

Thanks

Capture.JPG
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Explorer
Explorer
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Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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A second screenshot, when the wr_level error is trigerred.

 

According to the debug guide : 

 

If dbg_wrcal_start did not assert, the write leveling failure occurred after OCLKDELAYED calibration.

 

I'm in this case (PHASELOCK and DQSFOUND completed, dbg_wrcal_start did not assert), but OCLKDELAY calib start is low.

Capture2.JPG
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Explorer
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Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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Note there isn't pull up resistor on address, control and ck lines.
I'm not sure if i need it or not.

 

And ZQ pin on the DDR3 is not connected to external 240 ohm pullup... 

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Moderator
Moderator
3,387 Views
Registered: ‎11-28-2016

Re: MIG don't generate ddr3_clk

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Hello @pgrangeray,

 

All of the DDR3 design guidelines mentioned in UG586 starting on page 192 are required.  Specifically you mentioned not having termination on the address lines and the ZQ resistor on the DDR3 and these are fundamental requirements in order for the interface to work.  Please review all the design guidelines in UG586 such as the termination, line impedance, length matching, and make sure you include the FPGA pin propagation times when length matching your layout.  All of these have to be corrected in order to guarantee a stable interface. 

 

It's good that the example design is going through the calibration stages so that leads me to believe there's a configuration or clocking issue with your own design.  You can use the example design as a reference for your own design to see where things deviate.

Xilinx Employee
Xilinx Employee
3,281 Views
Registered: ‎10-19-2015

Re: MIG don't generate ddr3_clk

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Hey @ryana I was just rereading @pgrangeray's last post. I think what's happening is the example design is loaded on the board with the debug signals and the ILAs are shows a calibration failure during write leveling.
@pgrangeray, can you confirm that when you load the example design on the board you do not see init_calib_complete assert?
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Explorer
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Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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@mcertosi

 

exactly. I tried with my design and the example design.

But, as ZQ pin of DDR is not connected, it can't work (no?). I'm waiting a PCB correction and will retest it.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: MIG don't generate ddr3_clk

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Hi @pgrangeray 

The ZQ pin is very important and is required for write leveling calibration. The rest of the termination resistors on the address/command/control lines are important as well. Without them I anticipate calibration failures in other later stages of calibration. 

 

Since you are going to have to re-spin the board to fix the termination, I wanted to highlight another often overlooked point with our routing guidelines so that you can verify this is included in your next revision. Please take care to fully understand the routing guidelines as adherence to all these guidelines will give you the maximum probability of success for your interface. Also feel free to either continue this thread or make a new thread if you are confused with any of the guidelines. 

 

It is required to include the FPGA package delays when calculating total electrical propagation delay. The routing guidelines in the Trace Lengths section of UG586 page 198 say the following: 

 

The trace lengths described here are for high-speed operation. The package delay should
be included when determining the effective trace length. Note that different parts in the
same package have different internal package skew values. De-rate the minimum period
appropriately in the MIG Controller Options page when different parts in the same
package are used.

 

And then 

 

These rules indicate the maximum electrical delays between DDR3 SDRAM signals:
• The maximum electrical delay between any DQ or DM and its associated DQS/DQS# must
be ≤ ±5 ps.

 

• The maximum electrical delay between any address and control signals and the
corresponding CK/CK# must be ≤ ±25 ps, with 8 ps being the optimal target.

 

• CK/CK# signals must arrive at each memory device after the DQS/DQS# signals. The
skew allowed between CK/CK# and DQS/DQS# must be bounded between 0 and
1,600 ps. The recommended skew between CK/CK# and DQS/DQS# is 150 ps to
1,600 ps for components/UDIMMs and for RDIMMs it is 450 ps to 750 ps. For DIMM
modules, the total CK/CK# and DQS/DQS# propagation delays from the FPGA to the
memory components on the DIMM must be accounted for when designing to this
requirement.

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Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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HI @mcertosi

 

I have now a new board with ZQ pin connectes to 240 ohm resistor.

 

But, it seems to be the same ... wrlvl_err ...

 

 By measuring DQS frequency, I get 3 MHz ... DQ pins stay at 340mV.

 

My clk_ref is 200MHz and sys_clk is 250MHz. PHY to clock ratio 4:1.

 

Something strange no?

 

wr_lvl_erro is raised when wl_edge_detect_valid is high too long (see my screenshot in previous page).

 

EDIT :

 

I added a timing delay constraint on CK outputs : 150 ps.

set_output_delay 150.000 [get_ports {{ddr3_ck_n[0]} {ddr3_ck_p[0]}}]

 

I reach the Write Calibration state now, when I reprogram the target. If i make a reset, I stop in Write leveling.

 

 

 

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Xilinx Employee
Xilinx Employee
2,692 Views
Registered: ‎10-19-2015

Re: MIG don't generate ddr3_clk

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Hi @pgrangeray

Are your address lines terminated now also? 

Are all the traces length matched and include the package delay of the FPGA?

Can you measure the power rails on the FPGA? 

Write Leveling failures normally indicate a fundamental failure. Skew, Power, ACC termination, are all critical. 

Measuring DQS frequency might not be a good measure, DQS is a strobe and not constantly on. Can you measure CK? 

-M 

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Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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@mcertosi

 

I now can reach the init_calib_complete!

I don't know how, maybe because i raise the CK delay.

 

But i have a tg_compare_error.

 

Adress lines are not terminated. Direct from FPGA to RAM (there are very close, approx 5mm).

Trace lengths are not calculated to match the delay requirement (so i add a delay on CK).

 

what do you mean about FPGA rails?

 

My oscilloscope is limited to 100MHz, i see nothing on DDR3_CLK...

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: MIG don't generate ddr3_clk

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Hi @pgrangeray

I wouldn't say that the goal of this thread is to pass manipulate the IP into passing calibration. Calibration errors are more like a symptom of a bigger problem on the PCB. 

 

 

How did you raise the CK delay? 

Did you change anything from the way the IP's RTL was generated by the Xilinx tools? 

What speed are we running the interface at? I'm worried about the 1000MHz sampling rate of the scope.

 

 

I've never seen an interface operate successfully without proper termination on the address traces. 

In this context the FPGA rails is the power pins. There should be a VCC_AUX and VCC_IO for the bank that the memory IP is placed in.

 

-M

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Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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@mcertosi

 

I didn't change anything on the MIG.

 

For the delay i added this constraint : 

 

set_output_delay 500.000 [get_ports {{ddr3_ck_n[0]} {ddr3_ck_p[0]}}]

 

What do you mean with adress termination. 50 ohm pull-up resistor do Vdd/2?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: MIG don't generate ddr3_clk

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@pgrangeray

I don't if that constraint will do anything, but its intent is to manipulate the IP from its default configuration. Would you mind removing that constraint for the rest of this debug?

The address termination is a 50Ohm resistor to Vdd/2.

Do you know if you accounted for FPGA package delay when doing your trace length matching calculations for your PCB layout? 

-M

 

 

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Re: MIG don't generate ddr3_clk

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@mcertosi

 

Termination resistors can be solder, print are ready on the PCB.

 

There is no trace length calculation... I didn't design the board, i'm just in charge of the software.

 

I will try without th econstraint.

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Xilinx Employee
Xilinx Employee
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Re: MIG don't generate ddr3_clk

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Hi @pgrangeray

Based on the information provided and the failure symptoms this appears to be a PCB problem. 

I'm not sure what you are saying about the termination resistors and print on the PCB, I apologize. 

 

Does your PCB engineer or team have an account for these forums? It would be good to get them involved in this discussion. 

Is this a Xilinx development board? 

 

Regards,

Matt 

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Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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Hi @mcertosi

 

The routing software (Design spark) gives me the trace length (in mm) :

 

Addr 0 : 12.74

Addr : 1 13.015

Addr 2 : 7.997

Addr 3 : 7.875

Addr 4 : 16.575

Addr 6 : 11.485

Addr 7 : 12.6

Addr 8 : 14.991

Addr 9 : 15.289

CK_n : 19.962

CK_p : 19.35

DQS_n_0 : 12

DQS_p_0 : 14.796

DQS_n_1 : 16.831

DQS_p_1 : 18

 

From you, is it ok?

 

For resistor termination, i would say we planned to put 50 ohm termination. But they are not welded (so there isn't pull-up). We can add it if necessary.

 

If i remove the timing constraint, it works if i select Internal termination Inpedance = 40 ohm. I have Init_calib_complet but tg_compare_error.

 

From Micron technical note ( Here)  : 

 

For point-to-point applications, a 34Ω driver with a 40Ω transmission line and a 60Ω termination provides the best, or near-best, solution. There is some mismatch, but with the DRAM and controller packages included, it provides the best solution. The four cases in the table below all provide good results. There is no crosstalk in these four cases, which must be considered as well. The more mismatch in the termination, the more crosstalk.

 

Is it related ton "IN TERMINATION" in the MIG configurator?

 

I attached schematics from Micron. what type topology should i use? I have only one single RAM component.

 

Capture.JPG
Capture2.JPG
Capture3.JPG
Capture4.JPG
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: MIG don't generate ddr3_clk

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Hi @pgrangeray

The first step is getting the trace lengths from the routes on the PCB, like you have provided. The second step is to export the package delays from the Vivado tool. Package delays are the effective trace length inside the FPGA, or the distance between the output buffer and the pin. This distance needs to be added to each trace length and then the overall length of the trace length + FPGA package delay needs to adhere to our skew guidelines. Go to an implemented Vivado project and use the tcl command write_csv -file <filename> to get the FPGA package delays. 

It seems like FPGA package delay was not accounted for in this design and that can cause problems. 

 

The address lines must be terminated. Please populate the all of the termination resistors on the address command control line. 

 

Be careful not to get caught in the calibration trap, if init_calib_complete asserts but tg_compare error also asserts, the interface is not fixed, nor is it safe to assume that we have made any tangible progress towards the root cause of the failure or improved the overall reliability of the system. 

 

Internal termination is for the FPGA. The DQ and DQS traces transfer data in both directions and there must be termination on each end so the internal termination impedance is for the data coming from the DRAM to the FPGA. It is unclear why the calibration passes when changing the internal termination values, however the issues that will have a larger impact on the interface are address termination resistors. We should fix that first, then retest. 

 

-M 

 

 

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Re: MIG don't generate ddr3_clk

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@mcertosi

 

OK. I will do that.

 

About termination resistor, when you say address command and control, you mean :

- addr 0 to 13

- cas / ras / we

- bank 0 to 2

 

What about CKE / ODT / CS? No Termination resistor ?

 

Package trace delay : 

[Min ,        Max,         Name]

127.211,   128.489,,,ddr3_addr[12]

125.568,   126.830,,,ddr3_addr[10]

127.532,   128.814,,,ddr3_addr[11]

121.556,   122.777,,,ddr3_addr[9]

110.237,    111.345,,,ddr3_addr[8]

112.513,    113.644,,,ddr3_addr[7]

93.472,      94.411,,,ddr3_addr[6]

95.264,      96.222,,,ddr3_addr[5]

100.100,    101.106,,,ddr3_addr[4]

95.568,      96.528,,,ddr3_addr[3]

93.597,      94.537,,,ddr3_addr[2]

99.974,      100.978,,,ddr3_addr[1]

103.636,    104.677,,,ddr3_addr[0]

 

90.189,      91.095,,,ddr3_ba[2]

91.742,     92.664,,,ddr3_ba[1]

69.459,     70.157,,,ddr3_ba[0]

 

107.539,    108.620,,,ddr3_ck_n

106.094,    107.160,,,ddr3_ck_p

 

90.251,      91.158,,,ddr3_cke

 

106.594,    107.665,,,ddr3_dm[1]

73.942,      74.685,,,ddr3_dm[0]

 

100.297,   101.305,,,ddr3_dqs_n[1]

70.914,     71.627,,,ddr3_dqs_n[0

103.330,   104.368,,,ddr3_dqs_p[1]

75.089,     75.843,,,ddr3_dqs_p[0]

 

99.791,  100.794,,,ddr3_dq[15]
127.064,128.341,,,ddr3_dq[14]
119.016,120.212,,,ddr3_dq[13]
116.973,118.149,,,ddr3_dq[12]
118.598,119.790,,,ddr3_dq[11]
115.632,116.794,,,ddr3_dq[10]
118.964,120.160,,,ddr3_dq[9]
104.325,105.373,,,ddr3_dq[8]
73.631,74.371,,,ddr3_dq[7]
72.067,72.791,,,ddr3_dq[6]
63.746,64.387,,,ddr3_dq[5]
62.988,63.621,,,ddr3_dq[4]
81.425,82.243,,,ddr3_dq[3]
84.330,85.178,,,ddr3_dq[2]
98.273,99.261,,,ddr3_dq[1]
100.771,101.783,,,ddr3_dq[0]

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: MIG don't generate ddr3_clk

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Hi @pgrangeray

There are so many rules and suggestions on how to route a successful memory interface. Without experience, I would treat each one of the rules as non-negotiable. I'm thinking we can accelerate the time to resolution if I can talk to the hardware engineer who designed the board. 

 

Below I've copied in the termination rules. All single ended traces need to be terminated. ODT, CKE, CS, are all single ended signals. 

What is the data mask pin doing on the DRAM side? is it connected to the FPGA? Is it terminated? Is it not connected to the FPGA? What is the termination to ground? 

 

If you see any unpopulated capacitors or resistors around the interface, please let me know what those are. 

 

Termination
These rules apply to termination for DDR3 SDRAM:

Single ended 40Ω traces and termination are required for operation at 1,333 Mb/s and
higher. 50Ω is acceptable below 1,333 Mb/s. Figure 1-91 and Figure 1-92 are for 1,333
Mb/s and higher. 


• Differential 80Ω traces and termination are required for operation at 1,333 Mb/s and
higher. 100Ω is acceptable below 1,333 Mb/s. Figure 1-93 is for 1,333 Mb/s and higher.


• When using a VTT supply, care must be taken to manage the high frequency currents
from the terminations. Bypass caps recommendation 1 μF for every four terminations
and 100 μF for every 25 terminations evenly distributed relative to the terminations. A
planelet should also be used to distribute power to the terminations.


• Address and control signals (A, BA, RAS_N, CAS_N, WE_N, CS_N, CKE, ODT)
are to be terminated with the onboard DIMM termination. If DIMM termination does
not exist or a component is being used, a 40Ω pull-up to VTT at the far end of the line
should be used (Figure 1-91). Except for the CK/CK_N which requires a differential
termination as shown in Figure 1-93.


• A split 80Ω termination to VCCO and a 80Ω termination to GND can be used
(Figure 1-92), but takes more power. For bidirectional signals, the termination is
needed at both ends of the signal. ODT should be used on the memory side. For best
performance in HP banks, DCI should be used. For best performance in HR banks,
IN_TERM (internal termination) should be used.

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Re: MIG don't generate ddr3_clk

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Hi @mcertosi

Board designer is on holidays this week.

But I have schematics.

 

I can add pull up to Vtt on address on single ended signals and clock. But for DQS there isn't differential termination, only pull up to Vtt...

Data mask is connected, dm_0 and dm_1.

What abour DQ 0 to 15? ODT isn't supported by the MIG. Should I add pull up to Vtt? Rules on UG586 doesn't talk about DQ lines.

 

There isn't capacitors...

 

I attach the schematic.

For the moment, resistors on the schematic are not on the board. I will try to add it.

 

I think design must be redone... 

 

In the SP605 design, CLK_p and CLk_n are connected with 100 ohm resistor. In Micro guide, I see CLK_p and CLK_n connected to Vtt via 39 ohm resistor and 0.1uF capacitor.

Wich one should  I use? 100 ohm is easier for me.

ODT Reset and CS_n are pulled to ground with 4.7Kohm resistor. Unfortunately i can't do it.

 

Thank you @mcertosi

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Explorer
Explorer
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Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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Hi @mcertosi

 

I have now 50 ohm resistor to Vtt on address, ras, cas, we, cs, reset_n and odt. And 100 ohm betweend ck_p and ck_n.

 

DM, DQ nad DQS are direct from FPGA to DDR3.

 

And no change. I have tg_compare_error high, and init_calib_complete high.

 

I am lost. I can't do more, excepting redesign the board... My project is late, late, late...

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Re: MIG don't generate ddr3_clk

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Hello @pgrangeray

Based on what we've discussed I'm am surprised you see init_calib_complete assert. Did you add the delay constraint back in?

 

The trace lengths need to be deskewed and need to include the package delays. 

If the hardware guidelines are not followed we can't fix the IP with code. 

 

The fastest path to resolution is to redesign the board and meet all of our design guidelines. 

The slower path is to send me your board files so I can review and then confirm that you need to follow all our design guidelines. We will follow the debugging guide in UG586. This debugging process will use an example design, and we will exchange ILA captures, PCB files, and your schematic files. I will try to isolate the most likely root cause of the failure and then ultimately recommend that the board gets redesigned following all of our guidelines. 

 

The path forwards with the lowest risk and the quickest product release is to redesign the board to meet all of our stated design guidelines I can look over the PCB and schematic files with you and we can evaluate the chance for future success. 

 

You mentioned earlier that there are no capacitors in the design. I hope that is not true, however if it is please be aware that the FPGA power requirement is 2% ripple voltage from the DC operating point. The typical DDR ripple voltage is 60mV, however our guidelines recommend 2% from the operating point there as well. Capacitors help with that ripple. 

 

The top 3 contributors are likely trace length matching, power ripple, termination. 

 

Also make sure to watch out that you are not changing PCB levels too much. Finally, make sure you have plenty of additional ground vias around the DRAM for better signal integrity. 

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Explorer
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Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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We redesign the board, respecting requirements (length, impedance).

 

Test in few weeks!

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Xilinx Employee
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Registered: ‎10-19-2015

Re: MIG don't generate ddr3_clk

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@pgrangeray Sounds good, I hope it works. Let me know if not! 

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Explorer
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Registered: ‎05-31-2017

Re: MIG don't generate ddr3_clk

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@mcertosi

 

HI, i've received the new board.

I program the MIG example design and it seems to work (init_calib_complete, app_rdy, etc.).

But in my project, i don't reach the init_calib_complete...

 

I open a new topic... 

 

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