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Visitor mysoul
Visitor
671 Views
Registered: ‎03-15-2018

MIG initialization failed in simulation

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Hi everyone,

 

I have a MIG 3.6 series, a DDR2 MT4HTF3264HY-53E, and an virtex-5 XC5VLX110T.

In simulation, use the file sim.do, MIG initialize the DDR, write and read data. it's ok.

I want to design a verilog module to control the write and read behavior.
I add the verilog file in rtl folder of user design and generate a testbench in ISE software.
In this testbench, I only give the sys_clk, idly_clk_200 and sys_rst_n signal, other signal equal 0.
I use the 200MHz for sys_clk and idly_clk_200, sys_rst_n actived for 1 us.

But in simulation, I have some trouble.

----The phy_init_done stay low.



Is there something to do?

Thanks guys.


This si my testbench module and datasheet for IP core.

`timescale 1ns / 1ps
    initial begin
        // Initialize Inputs
        sys_clk = 0;
        idly_clk_200 = 0;
        sys_rst_n = 0;
        app_wdf_wren = 0;
        app_af_wren = 0;
        app_af_addr = 0;
        app_af_cmd = 0;
        app_wdf_data = 0;
        app_wdf_mask_data = 0;
        #1000 sys_rst_n = 1;

        // Wait 100 ns for global reset to finish
        #100;
        
        // Add stimulus here

    end
    
always #5 sys_clk = ~sys_clk;
always #2.5 idly_clk_200 = ~idly_clk_200;

CORE Generator Options:
   Target Device                  : xc5vlx110t-ff1136
   Speed Grade                    : -2
   HDL                            : verilog
   Synthesis Tool                 : ISE

MIG Output Options:
   Module Name                    : ddr2
   No of Controllers              : 1
   Selected Compatible Device(s)  : --
   Hardware Test Bench           : disabled
   PPC440                         : --
   PowerPC440 Block Selection     : --

FPGA Options:
   PLL                            : enabled
   Debug Signals                  : Disable
   System Clock                   : Single-Ended
   Limit to 2 Bytes per Bank      : disabled

Extended FPGA Options:
   DCI for DQ/DQS                 : enabled
   DCI for Address/Control        : disabled
   Class for Address and Control  : Class II

Reserve Pins:
   --
    
   /*******************************************************/
   /*                  Controller 0                       */
   /*******************************************************/
   Controller Options :
      Memory                         : DDR2_SDRAM
      Design Clock Frequency         : 5000 ps(200.00 MHz)
      Memory Type                    : SODIMMs
      Memory Part                    : MT4HTF3264HY-53E
      Equivalent Part(s)             : --
      Data Width                     : 64
      Memory Depth                   : 1
      ECC                            : ECC Disabled
      Data Mask                      : enabled

   Memory Options:
      Burst Length (MR[2:0])         : 4(010)
      Burst Type (MR[3])             : sequential(0)
      CAS Latency (MR[6:4])          : 3(011)
      Output Drive Strength (EMR[1]) : Fullstrength(0)
      RTT (nominal) - ODT (EMR[6,2]) : 75ohms(01)
      Additive Latency (EMR[5:3])    : 0(000)

   FPGA Options:
      IODELAY Performance Mode       : HIGH

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1 Solution

Accepted Solutions
Moderator
Moderator
883 Views
Registered: ‎02-11-2014

Re: MIG initialization failed in simulation

Jump to solution

Hello @mysoul,

 

If you only have a clock stimulus in your test bench and you don't instantiate the memory model then you will not be able to calibrate MIG in simulation. Please look at what the sim_tb_top.vhd file is doing and then use that logic in your own test bench.

 

Thanks,

Cory

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2 Replies
Moderator
Moderator
884 Views
Registered: ‎02-11-2014

Re: MIG initialization failed in simulation

Jump to solution

Hello @mysoul,

 

If you only have a clock stimulus in your test bench and you don't instantiate the memory model then you will not be able to calibrate MIG in simulation. Please look at what the sim_tb_top.vhd file is doing and then use that logic in your own test bench.

 

Thanks,

Cory

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Visitor mysoul
Visitor
613 Views
Registered: ‎03-15-2018

Re: MIG initialization failed in simulation

Jump to solution

Thanks for your reply, I solved this problem. Because I don't instantiate the memory model.

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