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Explorer
Explorer
755 Views
Registered: ‎05-31-2017

MIG not ready for a long time, why?

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Hi,

 

I simulate a video stream rotation with DDR3. I 

I use a XC7A50T-3.

I am in 4:1 mode.

 

I simulation, with Micron DDR3 simulation file. 

app_rdy and app_wdf_rdy are not high at the same time. So i need to wait a long time before sending commands.

In this configuration, data rate isn't sufficient for my application.

 

Maybe it is my way to send command to MIG that is not good.

 

Someone can help me?

 

In the TCL console, ddr3_sim tells :

 

tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220602078.0 ps INFO: Activate bank 1 row 0000
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220617078.0 ps INFO: Activate bank 0 row 0000
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220622709.0 ps INFO: Write bank 1 col 008, auto precharge 0
tb_top_sim_top.ddr3_sim_0.main: at time 220630201.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220637709.0 ps INFO: Write bank 0 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220645201.0 ps INFO: Write bank 0 col 008, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220652709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220660201.0 ps INFO: Write bank 1 col 008, auto precharge 1
tb_top_sim_top.ddr3_sim_0.main: at time 220682709.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 220693955.0 ps INFO: Auto Precharge bank 1
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220693955.0 ps INFO: Precharge bank 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220722078.0 ps INFO: Activate bank 1 row 0002
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220742709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220750201.0 ps INFO: Write bank 1 col 008, auto precharge 1
tb_top_sim_top.ddr3_sim_0.main: at time 220750201.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 220772709.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 220783955.0 ps INFO: Auto Precharge bank 1
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220812078.0 ps INFO: Activate bank 1 row 0004
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220832709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220840201.0 ps INFO: Write bank 1 col 008, auto precharge 1
tb_top_sim_top.ddr3_sim_0.main: at time 220840201.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 220862709.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 220873955.0 ps INFO: Auto Precharge bank 1
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220902078.0 ps INFO: Activate bank 1 row 0006
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220922709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220930201.0 ps INFO: Write bank 1 col 008, auto precharge 1
tb_top_sim_top.ddr3_sim_0.main: at time 220930201.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 220952709.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 220963955.0 ps INFO: Auto Precharge bank 1
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 220992078.0 ps INFO: Activate bank 1 row 0008
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221012709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221020201.0 ps INFO: Write bank 1 col 008, auto precharge 1
tb_top_sim_top.ddr3_sim_0.main: at time 221020201.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 221042709.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 221053955.0 ps INFO: Auto Precharge bank 1
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221082078.0 ps INFO: Activate bank 1 row 000a
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221102709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221110201.0 ps INFO: Write bank 1 col 008, auto precharge 1
tb_top_sim_top.ddr3_sim_0.main: at time 221110201.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 221132709.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 221143955.0 ps INFO: Auto Precharge bank 1
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221172078.0 ps INFO: Activate bank 1 row 000c
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221192709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221200201.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.main: at time 221200201.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221207709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221215201.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221222709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221230201.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221237709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221245201.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221252709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221260201.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221267709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221275201.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221282709.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221290201.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221297709.0 ps INFO: Write bank 1 col 008, auto precharge 1
tb_top_sim_top.ddr3_sim_0.main: at time 221320201.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
tb_top_sim_top.ddr3_sim_0.main: at time 221331463.0 ps INFO: Auto Precharge bank 1
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221359586.0 ps INFO: Activate bank 1 row 000e
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221380201.0 ps INFO: Write bank 1 col 000, auto precharge 0
tb_top_sim_top.ddr3_sim_0.cmd_task: at time 221387709.0 ps INFO: Write bank 1 col 008, auto precharge 1
tb_top_sim_top.ddr3_sim_0.main: at time 221387709.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm

 

Why multiple write (in red color)?

I send the same write command and i get multiple write!

It ties in the long time MIG is not ready.

 

To see screenshot in large size :

https://image.ibb.co/nGRjs7/Capture.jpg

 

Capture.JPG
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1 Solution

Accepted Solutions
Explorer
Explorer
1,010 Views
Registered: ‎05-31-2017

Re: MIG not ready for a long time, why?

Jump to solution

By modifing my writing process, i manage to obtain 300Mo/s (by changing row every write command), and 1366Mo/s peak datarate reading (in simulation).

 

So i think the problem is solved!

 

Thanks everyone!

3 Replies
Scholar drjohnsmith
Scholar
746 Views
Registered: ‎07-09-2009

Re: MIG not ready for a long time, why?

Jump to solution

Have a quick look at the simulation example you can generate from the core.

 

I seem to remember a speed up generic that can be set for simulation,

 

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Explorer
Explorer
718 Views
Registered: ‎05-31-2017

Re: MIG not ready for a long time, why?

Jump to solution

Hi @drjohnsmith

 

Example design is not very helpful...

 

I don't know if the ddr simulation has some mistakes, but data and address are not coherent.

I think the column number is writed in data, but there is a shift...

 

When app_rdy is low, data are sent if app_wdf_rdy is high. 

When app_wdf_rdy is low and app_rdy is high, command are sent.

But how to keep consistency?

 

sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 78851201.0 ps INFO: Write bank 0 col 030, auto precharge 0
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 78858709.0 ps INFO: Write bank 0 col 038, auto precharge 0
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.main: at time 78858709.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78863402.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000030 data = 0030
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78864340.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000031 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78865263.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000032 data = 0030
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78866201.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000033 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 78866201.0 ps INFO: Write bank 0 col 040, auto precharge 0
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78867140.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000034 data = 0030
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78868078.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000035 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78869017.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000036 data = 0030
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78869955.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000037 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78870894.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000038 data = 0038
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78871832.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000039 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78872771.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000003a data = 0038
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78873709.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000003b data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 78873709.0 ps INFO: Write bank 0 col 048, auto precharge 0
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78874648.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000003c data = 0038
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78875586.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000003d data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78876525.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000003e data = 0038
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78877463.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000003f data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78878402.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000040 data = 0040
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78879340.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000041 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78880263.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000042 data = 0040
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78881201.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000043 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 78881201.0 ps INFO: Write bank 0 col 050, auto precharge 0
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78882140.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000044 data = 0040
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78883078.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000045 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78884017.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000046 data = 0040
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78884955.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000047 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78885894.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000048 data = 0048
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78886832.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000049 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78887771.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000004a data = 0048
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78888709.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000004b data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 78888709.0 ps INFO: Write bank 0 col 058, auto precharge 0
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78889648.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000004c data = 0048
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78890586.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000004d data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78891525.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000004e data = 0048
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78892463.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000004f data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78893402.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000050 data = 0050
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78894340.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000051 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78895263.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000052 data = 0050
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78896201.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000053 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 78896201.0 ps INFO: Write bank 0 col 060, auto precharge 0
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78897140.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000054 data = 0050
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78898078.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000055 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78899017.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000056 data = 0050
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78899955.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000057 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78900894.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000058 data = 0058
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78901832.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000059 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78902771.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000005a data = 0058
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78903709.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000005b data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 78903709.0 ps INFO: Write bank 0 col 068, auto precharge 0
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78904648.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000005c data = 0058
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78905586.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000005d data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78906525.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000005e data = 0058
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78907463.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000005f data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78908402.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000060 data = 0060
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78909340.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000061 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78910263.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000062 data = 0060
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.data_task: at time 78911201.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000063 data = 0000
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 78911201.0 ps INFO: Write bank 0 col 070, auto precharge 0

Capture.JPG
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Explorer
Explorer
1,011 Views
Registered: ‎05-31-2017

Re: MIG not ready for a long time, why?

Jump to solution

By modifing my writing process, i manage to obtain 300Mo/s (by changing row every write command), and 1366Mo/s peak datarate reading (in simulation).

 

So i think the problem is solved!

 

Thanks everyone!