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Explorer
Explorer
1,536 Views
Registered: ‎04-19-2016

MIG read & write latency may cause the HDMI video pattern is slowly changing

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Hello, 

 

  • I have an FMC HMDI-in for video-in and HDMI-out for video-out. I am using the MIG IP for PL-Side DDR3. And I am writing/reading to/from PL-DDR3 via MIG by using VDMAs. 
  • Axi-Stream --> 200MHz, Memory map--> 200MHz
  • I can see the HDMI-out video on my hdmi screen. But there is a problem, when changing the video-in pattern, on the screen pattern is very slowly changing. Entire new pattern is clealry visible (stable) on the screen after the 3-4 second that I have changed the pattern. 
  • What is possible reasons, I am thinking MIG Read latency. Possible?

Best Regards,

  

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1 Solution

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Moderator
Moderator
2,509 Views
Registered: ‎06-30-2010

Re: MIG read & write latency may cause the HDMI video pattern is slowly changing

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Sounds like the system latency. CAn you describe how the picture gets changed.....

Is the new picture then buffered in the memory and read out after the original picture is buffered out?
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3 Replies
Moderator
Moderator
2,510 Views
Registered: ‎06-30-2010

Re: MIG read & write latency may cause the HDMI video pattern is slowly changing

Jump to solution
Sounds like the system latency. CAn you describe how the picture gets changed.....

Is the new picture then buffered in the memory and read out after the original picture is buffered out?
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
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Explorer
Explorer
1,498 Views
Registered: ‎04-19-2016

Re: MIG read & write latency may cause the HDMI video pattern is slowly changing

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Hello @jheslip,

 

Is the new picture then buffered in the memory and read out after the original picture is buffered out? 

Obviously I could not get it above. But my picture write&read path is : 

I am using a Write VDMA to PL-side DDR3 and Read VMDA  from PL-side DDR3. I have used 3 frame buffer in each vdma.

  1. i.e : Write vdma starts to write to PL-DDR3 with beginning the address 0x40000000  by three frames, 
  2. then I am copying my frame sized memory content by beginning address 0x40000000 to adress 0x50000000,
  3. Read vdma starts to read from PL-DDR3 with beginning the address 0x50000000 by three frames

Picture changing is basicly like above. Probably you mean that there may be previous frames in one of the three frame buffers, when new frame comes. 

 

You know hdmi is required 148.5MHz clock for in and out . But Axi-Stream is needed to be the same 148.5MHz? Because I am running Axi-Stream and Memory-map 200MHz.

 

Best Regards,

 

 

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Explorer
Explorer
1,472 Views
Registered: ‎04-19-2016

Re: MIG read & write latency may cause the HDMI video pattern is slowly changing

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Hello @jheslip,

I have realized that copying an hdmi frame from one location to another in PL-side DDR3 spends nearly 1000ms. But each hdmi frame comes per 16ms. Problem is sourced this.

Regards,
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