11-29-2009 07:17 AM
i generate the ddr2 ip core ,then get example_design and user_design,when i download the bit file into the device ,i find that the init_done signal does not go high when i download the user_design.but if i download the example_design,the init_done signal go high!i want to know why?who help me?it trouble me for a long time!
11-29-2009 10:07 PM
Which simulator you are using ?
If its VCS then you need to check your script
Which Version of MIG you are using. Currently MIG 3.2 avaialble with ISE 11.2 so its recomanded to use latest
If you are using Mdelsim then Xilinx Provide sim.do file please compile this file and rerun the simulation
If you need further help then you can create a case Xilinx Tech support will help you
11-30-2009 09:07 AM