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Visitor captainjiang
Visitor
4,164 Views
Registered: ‎04-02-2009

MIG23 DDR2 init_done signal never go high in user_design

i generate the ddr2 ip core ,then  get example_design and user_design,when i download the bit file into the device ,i find that the init_done signal does not go high when i download the user_design.but if i download the example_design,the init_done signal go high!i want to know why?who help me?it trouble me for a long time!

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2 Replies
Xilinx Employee
Xilinx Employee
4,150 Views
Registered: ‎08-01-2008

Re: MIG23 DDR2 init_done signal never go high in user_design

Hi

 

Which simulator you are using ?

 

If its VCS then you need to check your script

 

Which Version of  MIG you are using. Currently MIG 3.2 avaialble with ISE 11.2 so its recomanded to use latest  

 

If you are using Mdelsim then Xilinx Provide sim.do file please compile this file and rerun the simulation

 

If you need further help then you can create a case Xilinx Tech support will help you

 

 

Thanks

Bala 

 

Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
4,130 Views
Registered: ‎10-23-2007

Re: MIG23 DDR2 init_done signal never go high in user_design

Are you hooking anything up to the use_design internal interface when you try it?  It won't work on its own.  That's what the example design does - it hooks up an internal test generator to talk to the internal interface of the memory controller.  Perhaps you already know this, but there isn't enough information in your post to be sure.
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