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Visitor fnmccs
Visitor
239 Views
Registered: ‎04-26-2013

MIG7 with AXI interface, read/write ordering.

Hello,

Maybe someone can help me out with this...

I have a Kintex-7 design with a DDR3 DRAM controller connected to assorted modules via an AXI crossbar. I need to be able to write a value to DRAM then read it back and guarantee that I get the new value. I.e. I need the read to happen after the write. Is it sufficient to wait for the AXI write-response before issuing the read or do I need to also set ORDERING=STRICT in the MIG?

The comments in axi_mc_b_channel.v say:

// ... If strict
// coherency is enabled (C_STRICT_COHERENCY == 1), then this module will
// monitor the MCB command/write FIFOs to determine when to send back the
// response. It will not send the response until it is guaranteed that the
// write has been committed completely to memory.

However I can find no other references to C_STRICT_COHERENCY and the mentions of a MCB suggest to me that these comments refer to devices with a hard memory controller. Is strict coherency not supported in Kintex7 I wonder?

 

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Moderator
Moderator
123 Views
Registered: ‎11-28-2016

Re: MIG7 with AXI interface, read/write ordering.

Hello @fnmccs ,

By nature of AXI protocol if you receive a valid Write Response from the controller then the command has been successfully ingested and scheduled by the controller and coherency is guaranteed. At that point if you issue the read command then controller will always guarantee coherency since it knows not to schedule the read ahead of the write since they're going to the same location. Nearly every system operates this way, otherwise you'll have indeterminate behavior.

Thanks,
Ryan.

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