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Visitor danhdoanes
Visitor
2,785 Views
Registered: ‎02-08-2017

Need help on QDRII+ implementation

Hi everyone,

I'm trying to interface with QDRII+ and I use NetFPGA-1G CML Kintex-7

I have done the simulation, it works just fine, however when I implement to the real board, the calibration is failed.

I have 2 questions:

  1. Do I need to use exact frequency for sys_clk_p/n (it requires 450.045 MHz)?
  2. In the NetFPGA board, I just see 1 pair system_clk_p/n (200MHz), I'm supposed to use it as clk_ref_p/n, what should I use for sys_clk_p/n(450.045MHz)

Thanks in advance.

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6 Replies
Xilinx Employee
Xilinx Employee
2,778 Views
Registered: ‎02-06-2013

Re: Need help on QDRII+ implementation

Hi

 

1.Yes the input clock period should be equal to the frequency you have selected during the core generation.

You can change the clock period during clock generation(set to 4000 or 2500 etc) so that you can see option of 5000ps(200Mhz) for input clock period so that you can use your available system clock on the board.

 

2. When you select 200Mhz for input clock the reference clock provides use system clock option so that it will use the input clock.

Regards,

Satish

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Visitor danhdoanes
Visitor
2,772 Views
Registered: ‎02-08-2017

Re: Need help on QDRII+ implementation

Thanks but I dont really understand your 2nd answer,

Can you explain it in more detail?

 

Regards,

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Xilinx Employee
Xilinx Employee
2,770 Views
Registered: ‎02-06-2013

Re: Need help on QDRII+ implementation

Hi

 

Check option 1 in below AR which applies to QDRII+ as well

 

https://www.xilinx.com/support/answers/43876.html

Regards,

Satish

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Visitor danhdoanes
Visitor
2,762 Views
Registered: ‎02-08-2017

Re: Need help on QDRII+ implementation

It's really helpful for me.

But when I try to implement to real board, calibration is still failed.

I use dbg_phy_status bits to light up a LED, but the result is that all the bit of dbg_phy_status is off. (at least, the bit 0 is off meanning that there are no problems with clock source and rst signal)

 

What should I do now?

 

Regards,

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Visitor danhdoanes
Visitor
2,706 Views
Registered: ‎02-08-2017

Re: Need help on QDRII+ implementation

Hi,

After carefully debugging, I found that the Stage 1 read calibration is started but it cannot finish.

Really need your advice.

 

Regards,

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Newbie qianyux
Newbie
874 Views
Registered: ‎04-02-2018

Re: Need help on QDRII+ implementation

hello,i am a student from China,and i study netfpga-1g-cml recently,can you tell me which  software simulation is used about netfpga,and is there other library file or something else need to be download?Thank you very much!

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