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Need something like a memory fence

Posts: 71
Registered: ‎09-25-2015

Need something like a memory fence

I have a topic that is MIG and HLS related. The topic is explained here: https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Need-something-like-a-memory-fence/m-p/747282/highlight/false#M8165


To me it looks, like memory operations are over optimized (within MIG) by letting overtake requests other request leaving a full pipeline of unprocessed requests behind.


  • At first: Is this assumption true for MIG4.0 (Vivado 2016.4) ?
  • Is there a solution to get a memory fence or marker inserted, so that one can be sure a memory write is done ?