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Visitor frac
Visitor
1,740 Views
Registered: ‎03-07-2018

PL DDR SI modeling failing for DQS lines

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We're seeing PL DDR DQS lines modeled in HyperLynx failing during reads. In particular, the DQS signal drops below the DC threshold due to what looks like excessive ringing. We have followed layout guidelines in UG583, and have experimented with longer traces in the layout and different on-die terminations on the DDR memory. However, we've not been able to get two out of four DQS lines to meet requirements. Attached are plots showing 1) a failing DQS line (first plot) and 2) a passing DQS line (DQS1). Any advice would be appreciated.

 

One question we have is, in HyperLynx, should we be probing at the pin or at the die?

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Moderator
Moderator
2,347 Views
Registered: ‎11-28-2016

Re: PL DDR SI modeling failing for DQS lines

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Hello @frac,

 

Those look like reflections from measuring at the FPGA pins and not at the FPGA die.  Because these FPGAs have large internal routing taking a DDR read measurement at the FPGA pins will look really bad because your probe point is not at the end of the transmission line.  Take a look at this Mentor article on how to setup HyperLynx to set the probe point at the FPGA die.

 

https://support.mentor.com/en/knowledge-base/MG83246

 

Mentor_Die_Article.PNG

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Moderator
Moderator
1,702 Views
Registered: ‎04-18-2011

Re: PL DDR SI modeling failing for DQS lines

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If you are using the DCI then the signal should be observed at the die to properly observe what's going on at the receiver
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Moderator
Moderator
2,348 Views
Registered: ‎11-28-2016

Re: PL DDR SI modeling failing for DQS lines

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Hello @frac,

 

Those look like reflections from measuring at the FPGA pins and not at the FPGA die.  Because these FPGAs have large internal routing taking a DDR read measurement at the FPGA pins will look really bad because your probe point is not at the end of the transmission line.  Take a look at this Mentor article on how to setup HyperLynx to set the probe point at the FPGA die.

 

https://support.mentor.com/en/knowledge-base/MG83246

 

Mentor_Die_Article.PNG

Visitor frac
Visitor
1,690 Views
Registered: ‎03-07-2018

Re: PL DDR SI modeling failing for DQS lines

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Hi @ryana

 

Thank you very much for the reply.

 

Do you happen to know if the same advice about probing at the die is valid for the PS side?

 

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Moderator
Moderator
1,688 Views
Registered: ‎11-28-2016

Re: PL DDR SI modeling failing for DQS lines

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Visitor frac
Visitor
1,686 Views
Registered: ‎03-07-2018

Re: PL DDR SI modeling failing for DQS lines

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Thank you very much. Much appreciated!

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Visitor frac
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1,655 Views
Registered: ‎03-07-2018

Re: PL DDR SI modeling failing for DQS lines

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Hi @ryana

 

BTW, would you recommend probing FPGA die to DDR pin or FPGA die to DDR die in the modeling, or does the answer depend on the nature of the DDR IBIS model?

 

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Moderator
Moderator
1,651 Views
Registered: ‎11-28-2016

Re: PL DDR SI modeling failing for DQS lines

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Hello @frac,

 

Here you would do the FPGA die and the DDR pin since the FPGA has those long package routes that result in poor signal integrity and the DDR packages have much smaller package routing that doesn't cause any issues.  Also the JEDEC spec defines all the timing requirements at the DDR pins and not the die.