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Partial reconfiguration of ddr3 core itself

Posts: 3
Registered: ‎02-25-2018

Partial reconfiguration of ddr3 core itself

Hi all


İ wonder, is it possible to apply partial reconfiguration to MIG ddr3 core itself. It contains a pll. But it can be placed to static region. Is it possible to put ddr3 core components other than the pll to PR region. Is virtex 6 contain hard ip for ddr3 controller or is it just a soft core generated from MIG? Is there any one tried it.




Posts: 353
Registered: ‎06-30-2010

Re: Partial reconfiguration of ddr3 core itself

can you give more detail on exactly what you are trying to do?
Are you trying to change the data rate of the interface?

The V6 controller is a soft core in the PL.
Don’t forget to reply, kudo, and accept as solution.