03-09-2018 08:26 AM
İ wonder, is it possible to apply partial reconfiguration to MIG ddr3 core itself. It contains a pll. But it can be placed to static region. Is it possible to put ddr3 core components other than the pll to PR region. Is virtex 6 contain hard ip for ddr3 controller or is it just a soft core generated from MIG? Is there any one tried it.
03-15-2018 08:11 AM