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Passing test from DDR controller generated by MIG

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Observer
Posts: 25
Registered: ‎03-12-2018
Accepted Solution

Passing test from DDR controller generated by MIG

I'm currently using Vivado 2017.3.1. I used MIG to generate a DDR controller (with targeted DDR3 memory). I'm using Modelsim as my simulation. In the example design, I ran the "sim.do" (with some minor changes to point to specific design files) and the simulation reported a test failure. Specifically, the simulation ran its course but the test checker stated that the DDR controller didn't calibrate and that caused the test failure. I presume I may have to play around with some generic settings in the example top-level file, but I'm not sure. Maybe a different of eyes will help. I enclosed a zip file of the ddr project. If you look towards the end of the sim.do file, you'll see what I mean where test failure is reported. Specifically, I'm getting "TEST FAILED: CALIBRATION DID NOT COMPLETE." Thanks for any help/suggestions/comments.


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Moderator
Posts: 272
Registered: ‎11-28-2016

Re: Passing test from DDR controller generated by MIG

Hello @bjackson_ost,

 

Think of it as Linux libraries, Python modules, or .Net versions.  Modelsim 6.6 looks like it came out in 2011 which makes it pretty old when you're trying to run it in tools from the 2017 time frame.  At that point any assumptions our tools make for the compiled Modelsim libraries or other functions that are assumed to be in 10.6b it's hard to expect that every single one would be present or behave exactly the same from a much earlier version of the software. 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

PG150 - UltraScale Memory Product Guide

UG583 - UltraScale Architecture PCB Design User Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide

View solution in original post


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Moderator
Posts: 272
Registered: ‎11-28-2016

Re: Passing test from DDR controller generated by MIG

Hello @bjackson_ost,

 

I took a look at your sim.do and your ddr_controller files and didn't see anything that caught my eye.  It would be good to know the behavior you're seeing when you try and run the simulation.  Such as if the initialization even starts or it gets stuck in a calibration stage.  It would also be good to know which version of Modelsim you're using since only 10.6b is officially supported with Vivado 2017.3.1.

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

PG150 - UltraScale Memory Product Guide

UG583 - UltraScale Architecture PCB Design User Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide

Observer
Posts: 25
Registered: ‎03-12-2018

Re: Passing test from DDR controller generated by MIG

Moderator
Posts: 272
Registered: ‎11-28-2016

Re: Passing test from DDR controller generated by MIG

Hello @bjackson_ost,

 

Currently you're using Modelsim 6.6a and that's not compatible with Vivado  2017.3.1.  Can you upgrade to Modelsim 10.6b and give it a try?

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

PG150 - UltraScale Memory Product Guide

UG583 - UltraScale Architecture PCB Design User Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide

Observer
Posts: 25
Registered: ‎03-12-2018

Re: Passing test from DDR controller generated by MIG

Hello, @ryana.

 

Thanks for the prompt reply. I'll see if my job would allow me to upgrade to 10.6b. In the meantime, could you explain to me why the Modelsim version matters? I ask because the files compile with no errors. It's just the matter that the testbench reports that the controller hasn't calibrated. Did I miss something?

Moderator
Posts: 272
Registered: ‎11-28-2016

Re: Passing test from DDR controller generated by MIG

Hello @bjackson_ost,

 

Think of it as Linux libraries, Python modules, or .Net versions.  Modelsim 6.6 looks like it came out in 2011 which makes it pretty old when you're trying to run it in tools from the 2017 time frame.  At that point any assumptions our tools make for the compiled Modelsim libraries or other functions that are assumed to be in 10.6b it's hard to expect that every single one would be present or behave exactly the same from a much earlier version of the software. 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

PG150 - UltraScale Memory Product Guide

UG583 - UltraScale Architecture PCB Design User Guide

UG586 - 7 Series FPGAs Memory Interface Solution User Guide

DDR3 and DDR4 Memory Interface Calibration and Hardware Debug Guide