12-06-2017 07:28 AM
My project using a K7-325 FPGA, and a DDR3 SO-DIMM connected to HR IO Banks(HP Banks are used by other devices). The clock of DDR is 400MHz. I use Vivado 2016.2 to compile my project, the operation is sequence write to entire DDR3, then sequence readout.
The question is that, on some specified address, the data are actually readed from another address in some chance(about 1/10). The same for write operation, when writing to some specified addresses, the data actually written to another address. The problem covers about 1/5 of entire address space, and there are no obvious rule of how error addresses are distributied. In other addresses, read/write are always no error repeatedly.
I suspect it caused by signal integrity, so I measured address and command signal from SO-DIMM card interface by a 4GHz oscilloscope. The signal looks well, clocks are crossed on almost center of most of address/command signal.
I tried to change another DDR3 SO-DIMM, change another FPGA, and reduce DDR clock from 400MHz to 312.5MHz. All lead to the same result.
I use only constraints generated by MIG, and not use any constrants for DDR. The Timing are completely met.
Another strange question. When I compile the same design using Vivado 2017.3, the DDR calibration cannot complete.
Anyone know why? Thanks for any input.
12-06-2017 11:37 AM
Hello, I would also suspect SI on your address/cmd/cntrl bus. When you look at the failing addresses, are their particular address bits that consistently fail and/or a particular address sequence? We frequently see crosstalk on address bits causing this type of failure. When you measure signal integrity, it would be best to trigger on the failing write to look at the suspect address bit(s). Or you could run a continual trigger on the suspect address bit(s) to look for crosstalk over time. Also, there are 3rd party crosstalk analysis tools where you can input your board files and get a report on crosstalk victims and aggressors.
Hope it helps.