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1,627 Views
Registered: ‎11-27-2017

Recommended HP banks for DDR3/DDR4

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Dear all,

 

my question is about Kintex Ultrascale XCKU035 / XCKU040, regarding to its compatibility with the use of two independent interface for DDR4. Specifically, we are thinking on SFVA784, FFVA900 and FFVA1156 packages. In the most simple case, we are thinking on use three HP banks for each DDR4 memory, six in total. At first, I have not found a document for a specific mapping recommendation of HP banks for DDR4. The related document I have found:

 

WP454, page 6: The graphic shows a memory configuration and bank distribution, but without the identification of the most appropiated banks for DDR3/DDR4 routing and performance. 

UltraScale_Memory_Interface_Capacities_v1p1.xlsm, the excel shows FPGA model and package capabilities, very interesting. However, not specific bank configuration is recommended. Furthermore, there are some differences between SFVA784 and FFVA900, when they have the same number of HP banks. For example, in the case of DDR4 64-bits > 512M. Why?

PG150, page 771: The image illustrates memory mapping for XCKU095 FFVA1156, and the following pages shows more configuration. This is what we are looking for. This index shows some memory mapping for these FPGA chips, specifically indicated due to some clock constraints of these chips.

 

As summary, my questions are:

- Recommendation / guidelines for bank selection in the case of two independent DDR4 memories for the XCKU035 / XCKU040 chips - SFVA784, FFVA900 and FFVA1156 packages.

- HP bank limitations for its application to DDR memories (case of FFVA900 with DDR3/DDR4 > 64 bits).

 

Each answer will be very appreciated!

Thank you very much!

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1 Solution

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Xilinx Employee
Xilinx Employee
2,330 Views
Registered: ‎06-30-2010

Re: Recommended HP banks for DDR3/DDR4

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There are no guidelines for picking one HP bank over the other except if they are needed to meet your interface needs or if the rest of the application has to use that bank. What I would do here is look at UG 575:  http://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf

 

And find the device/package combinations you want to use, we know you need 3 banks for each and they must be adjacent for a memory interface and in the same column. So looking at the screen shot below that means interface #1 is in Banks 66, 67 and 68 and for inetrface2 you have the option of bank 44, 415 and 46 or Banks 45, 46 and 47

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ddr.PNG
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3 Replies
Xilinx Employee
Xilinx Employee
1,611 Views
Registered: ‎08-01-2008

Re: Recommended HP banks for DDR3/DDR4

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you can get all the document here
https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0061-ultrascale-memory-interface-ddr4-ddr3-hub.html

https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0007-vivado-pin-planning-hub.html
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
2,331 Views
Registered: ‎06-30-2010

Re: Recommended HP banks for DDR3/DDR4

Jump to solution

There are no guidelines for picking one HP bank over the other except if they are needed to meet your interface needs or if the rest of the application has to use that bank. What I would do here is look at UG 575:  http://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf

 

And find the device/package combinations you want to use, we know you need 3 banks for each and they must be adjacent for a memory interface and in the same column. So looking at the screen shot below that means interface #1 is in Banks 66, 67 and 68 and for inetrface2 you have the option of bank 44, 415 and 46 or Banks 45, 46 and 47

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
ddr.PNG
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1,136 Views
Registered: ‎11-27-2017

Re: Recommended HP banks for DDR3/DDR4

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Dear Xilinx team,

 

the KCU105 uses the bank 45 as the input for system clock of 300MHz. The DDR4-64bit is placed also in this bank (as bank 44 and 46), and the clock output 1200MHz from FPGA to DDR4 is also placed in this bank. In our design, a new DDR4-64bit is placed in banks 66, 67 and 68. Our question is related about the possibilities: use the 300MHz clock from bank 45 for both banks, or use two independent 300MHz clock, each one for each DDR4-64bit bank. Which option do you consider as the best for a board design with 2 independent DDR4-64bit banks?

 

Thank you very much,

Antonio.

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