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SP605 DDR3 addressing

Posts: 26
Registered: ‎11-06-2015

SP605 DDR3 addressing

Hi, the following post is quite long, but since I have had trouble making the SP605 board properly interact with the DDR3 for over a month now, hopefully this will be useful to others in the same situation as I find myself in. I am pretty certain it's a simple configuration or conceptual error, but I would be more than happy to have this resolved soon.





I have created a USB-UART interface to communicate with the FPGA and control the DDR3. Using the IP generator in ISE, I generated a MIG wrapper and then I designed the memory interface controller. However, I have referenced manuals ug388 and ug416, but I have not been able to have the DDR3 behave as expected.





Playing around with the burst lengths for write and read commands, I am able to get data back from the DDR3, yet the addressing scheme does not seem to be correct as data is duplicated in addresses 0 and 1, 2 and 3, 4 and 5, and so forth. Also, whenever I write into address 0, for example, nothing changes. Then, when I write into address 1, both addresses 0 and 1 are updated with the data value I just sent. It seems I am "losing" half of the memory space due to this coupled effect.





The setup for the DDR3 using the IP generator – considering the SP605 board scenario – is listed below. In sum, I activated the DDR3 Bank 3 and configured Port0 to be 32-bit bidirectional.


Memory selection:

> Enable AXI interface: unchecked

> Use extended MCB performance range: unchecked

> Memory type for bank 3: DDR3 SDRAM

> Memory type for bank 1: none


Options for C3 – DDR3 SDRAM

> Frequency: 400 MHz

> Memory part: MTJ41J64M16XX-187E


Memory options for C3 – DDR3 SDRAM

> Output driver impedance control: RZQ/6

> RTT (nominal) – ODT: RZQ/4

> Auto self refresh: enabled


Port configuration for C3 – DDR3 SDRAM

> Two 32-bit bi-directional and four 32-bit unidirectional ports

> Port0: checked

> Port1: unchecked

> Port2: unchecked

> Port3: unchecked

> Port4: unchecked

> Port5: unchecked

> Memory address mapping selection: row-bank-column


FPGA options for C3 – DDR3 SDRAM

> Memory interface pin termination: Calibrated input termination

> Select RZQ pin location: R7

> Select ZIO pin location: W4

> Debug signals for memory controller: disable

> System clock: differential





From Matlab, I send in a 64-bit command which should write or read the DDR3 based on the address and data provided in this command.


wire [00:00] cmd_instruction = usb_data[63:63];          // ‘0’ = write; ‘1’ = read
wire [27:00] cmd_address = usb_data[62:37];             // 26-bit address
wire [31:00] cmd_data = usb_data[31:00];                   // 32-bit data


In ug388, the following can be extracted:


Page 20: The address is 26 bits wide.




> C_P0_DATA_PORT_SIZE = 32         // 32-bit data ports

> C_P0_MASK_SIZE = 4                      // 4 bytes = 32 bits (each mask bit represents an entire data byte)


Pages 26-27: Command data structure.

> pX_cmd_addr[29:0]: 30-bit address, however the last two bits should = “00” since every word (32 bits) is formed by 4 bytes.

> pX_cmd_bl[5:0]: Burst length of 1 is obtained by setting this signal to 0.

> pX_cmd_instr[2:0]: The only command instructions used are write=”000” and read=”001”.


Page 28: Write data structure.

> pX_wr_mask[PX_MASKSIZE-1:0]: 4-bit mask is set to “0000” so that all 4 bytes are always written into the memory.





Using all this information, I assigned my signals in the following manner:

assign p0_mcb_cmd_instr = {2'b00, cmd_instruction};
assign p0_mcb_cmd_addr = {2’d0, cmd_address, 2'd0};
assign p0_mcb_cmd_bl = 6'd0;

assign p0_mcb_wr_data = cmd_data;

assign p0_mcb_wr_mask = 4'd0;





Based on the configuration, does anyone know what the expected behavior of my controller should be?

If any additional information is necessary for clarification, please let me know.


Thanks a lot,


Posts: 26
Registered: ‎11-06-2015

Re: SP605 DDR3 addressing

One last thing:


Pages 51 and 61-62 give additional information as to the address mapping. Also, Table 4-5 (pg. 63) shows how the 2 MSBs and 2 LSBs for the "DDR3, x16, 1 Gb" should not be used and match the assignment in the Verilog code:


assign p0_mcb_cmd_addr = {2’d0, cmd_address, 2'd0};

Xilinx Employee
Posts: 4,131
Registered: ‎07-11-2011

Re: SP605 DDR3 addressing

[ Edited ]

@bpedroni, What is your memory burst length? There are known issues with IP accessing same addresses with BL4.

If it is 4 please try to set it for 8 and see how it goes





Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
Posts: 26
Registered: ‎11-06-2015

Re: SP605 DDR3 addressing

Hi @vsrunga,


The MIG already generated it set to 8.


localparam C3_MEM_BURST_LEN = 8;




Posts: 8
Registered: ‎03-13-2016

Re: SP605 DDR3 addressing

HI @bpedroni


My design is exactly same as your design, using USB-UART interface to communicate with the FPGA and control the DDR3. I am also facing same issue, data is duplicated in addresses 0 and 1, 2 and 3, 4 and 5, and so forth.


Have you got any solution? could you please share with me. it will be helpful for me. 

Posts: 26
Registered: ‎11-06-2015

Re: SP605 DDR3 addressing

Hi @mam12, I have been able to fix some things but there are still issues.


My current scenario (to which I have designed a "bug" workaround, yet taking up additional clock cycles) is the following:

* Bug 1: the DDR3 writes into the previous address speficied in cmd_address, so the write function shifts the address by 1.
* Bug 2: the last DDR3 read word is always incorrect, so the burst length and DDR3 read were adapted as to return only meaningful data (burstFIFO was created).


I would be happy to share my code with you and maybe we could help each other out. I plan on doing a Youtube tutorial on how to configure the DDR3 using Spartan-6 because it has been a nightmare.

Posts: 8
Registered: ‎03-13-2016

Re: SP605 DDR3 addressing

Hi @bpedroni


Thanks for reply.


Could you share your code so that i may get some ideas to solve the issues or even I would be happy to share my code with you. 

you can look at my code and let me know if any corrections are required. 


Its really good idea to do Youtube tutorial on configure the DDR3. It will help may people like me. 

Posts: 26
Registered: ‎11-06-2015

Re: SP605 DDR3 addressing



Hello, I have finally been able to configure the DDR3 appropriately and get reliable results. For my sake, I have written a walkthru of how to perform this configuration.


Therefore, I was wondering if it would be OK with you guys (i.e. Xilinx) if I attach the PDF here in the forum so others can benefit from my experience in this issue.




Posts: 3,070
Registered: ‎02-06-2013

Re: SP605 DDR3 addressing



Feel free to share any docs you want to share that will help other users on similar issue. 



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