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Visitor lingaraj
Visitor
104 Views
Registered: ‎01-31-2019

Self request entry and exit in ddr4

To perform Self refresh entry/exit as per the specification pg150, it is mentioned that mem_init_skip and app_restore_en signal has to be assert.

is it really required to assert the app_restore_en signal/ can we skip restore and still exit self refresh?  

 

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4 Replies
Xilinx Employee
Xilinx Employee
68 Views
Registered: ‎08-21-2007

回复: Self request entry and exit in ddr4

Yes. The self-refresh feature always comes up with the save/restore feature and is not available alone.

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Visitor lingaraj
Visitor
53 Views
Registered: ‎01-31-2019

回复: Self request entry and exit in ddr4

Thanks for the response,

I have some queries.

To perform save restore operation is it mandatory to do reset operation?

I am able to read the calibration data with XSDB ports when I put it in self refresh. is it possible to restore the calibration data with XSDB ports without reset?

If reset is mandatory, we will lose the data which we already stored in the memory. is there any other way to retain the data with self refresh entry and exit?

It is better if you share KT on how to access Mode Register.

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Xilinx Employee
Xilinx Employee
43 Views
Registered: ‎08-21-2007

回复: Self request entry and exit in ddr4

Are you talking about the reset of DDR4 IP? When the DDR4 has been in self-fresh mode, the data will be safe. 

As per the DRAM protocol, the memory interface signals cke and reset_n must be maintained at 0 and 1 values respectively to keep the DRAM in self-refresh mode.

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Visitor lingaraj
Visitor
38 Views
Registered: ‎01-31-2019

回复: Self request entry and exit in ddr4

Yes exactly,

Please find the attachment below. there he mentioned that mem_init_skip and app_restore_en has to be assert within 50 interconnect cycles after the user interface reset is deasserted in the self refresh exit cycle.

reset_issue_xilinx.PNG
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